Home » Archimedes archive » Acorn Computing » 1994 09 subscription disc.adf » 9409s » MEMCPatch/MEMCPatSrc
MEMCPatch/MEMCPatSrc
This website contains an archive of files for the Acorn Electron, BBC Micro, Acorn Archimedes, Commodore 16 and Commodore 64 computers, which Dominic Ford has rescued from his private collection of floppy disks and cassettes.
Some of these files were originally commercial releases in the 1980s and 1990s, but they are now widely available online. I assume that copyright over them is no longer being asserted. If you own the copyright and would like files to be removed, please contact me.
| Tape/disk: | Home » Archimedes archive » Acorn Computing » 1994 09 subscription disc.adf » 9409s |
| Filename: | MEMCPatch/MEMCPatSrc |
| Read OK: | ✔ |
| File size: | 1512 bytes |
| Load address: | 0000 |
| Exec address: | 0000 |
File contents
10REM > MEMCPatSrc
20DIM code &400
30
40sp = 13
50lr = 14
60pc = 15
70
80Service_Reset = &27
90V_FLAG = 1<<28
100
110FOR pass=0 TO 3 STEP 3
120P%=code
130[OPT pass
140.module_base
150 DCD 0
160 DCD initialise - module_base
170 DCD finalise - module_base
180 DCD service - module_base
190 DCD title_string - module_base
200 DCD help_string - module_base
210 DCD help_table - module_base
220
230; ---------------------------------------------------------------------------------------------------------
240
250.initialise
260 STMFD sp !, {lr}
270 BL claim_swi_vector
280 LDMFD sp !, {pc}
290
300; ---------------------------------------------------------------------------------------------------------
310
320.finalise
330 STMFD sp !, {lr}
340 BL release_swi_vector
350 LDMFD sp !, {pc}
360
370; ---------------------------------------------------------------------------------------------------------
380
390.service
400 CMP r1, #Service_Reset
410 MOVNES pc, lr
420 STMFD sp !,{r0-r5,lr}
430 BL claim_swi_vector
440 LDMFD sp !,{r0-r5,pc}^
450
460; ---------------------------------------------------------------------------------------------------------
470
480.title_string
490 EQUS "MEMCPatch":DCB 0
500
510.help_string
520 EQUS "MEMC Patch":EQUB 9::EQUS "1.01 (27 Nov 1993)":EQUB 0
530.help_table
540 EQUS "PatchingMEMC"
550 EQUB 0:ALIGN
560 EQUD 0
570 EQUD 0
580 EQUD 0
590 EQUD help_text - module_base
600.help_text
610 EQUS "The MEMC Patch module prevents the setting of bit 6 of the MEMC":EQUB 13
620 EQUS "control register which otherwise crashes the machine.":EQUB 0
630 ALIGN
640
650; ---------------------------------------------------------------------------------------------------------
660
670.release_swi_vector
680 MOV r0, #8
690 LDR r1, [r0]
700 LDR r2, new_branch ; check that our SWI decoder hasn't been replaced
710 CMP r1, r2
720 LDREQ r1, old_branch ; replace original decoder if it hasn't
730 STREQ r1, [r0]
740 MOVEQ r0, #0
750 STREQ r1, old_branch
760 MOVEQS pc, lr
770
780 LDR r2, old_branch ; if the old branch is already there then do nothing
790 CMP r1, r2
800 MOVEQS pc, lr
810
820 ADR r0, error_block ; otherwise return an error
830 ORRS pc, lr, #V_FLAG
840
850.error_block DCD &103
860 EQUS "Can't detach SWI handler":DCB 0
870 ALIGN
880
890; ---------------------------------------------------------------------------------------------------------
900
910.claim_swi_vector
920 MOV r0, #8
930 LDR r0, [r0] ; get branch to SWI handler
940 STR r0, old_branch
950
960 ADR r1, second_branch-8 ; insert in our own code
970 SUB r0, r0, r1, LSR #2
980
990 BIC r0, r0, #&FF000000 ; handle SUB overflow for when old branch < replacement.
1000 ORR r0, r0, #&EA000000
1010
1020 STR r0, second_branch
1030
1040 ADD r0, r0, #(second_branch-first_branch) / 4
1050 SUB r0, r0, #&D0000000
1060 STR r0, first_branch ; convert to a BNE
1070
1080 MOV r1, #8
1090 ADR r0, swi_patch-8-8
1100 MOV r0, r0, LSR #2
1110 ADD r0, r0, #&EA000000
1120 STR r0, [r1]
1130 STR r0, new_branch ; put in a branch to our code
1140
1150 MOVS pc, lr
1160
1170; ---------------------------------------------------------------------------------------------------------
1180
1190.swi_patch
1200 STMFD sp !,{lr}
1210 BIC lr, lr, #&FC000003
1220 LDR lr, [lr,#-4] ; get SWI instruction
1230
1240 BIC lr, lr, #&FF000000
1250 BIC lr, lr, #&20000
1260
1270 CMP lr, #&1A ; is it OS_UpdateMEMC ?
1280 LDMNEFD sp !, {lr} ; otherwise drop through to SWI handler
1290.first_branch
1300 DCD 0
1310
1320 ANDS lr, r0, #1<<6 ; is bit 6 of new data set ? If so Z=FALSE else Z=TRUE
1330 BEQ continue ; if bit 6 is not set then Z=TRUE and drop through to OS_UpdateMEMC
1340 ANDS lr, r1, #1<<6 ; is bit 6 of mask set ? If so Z=FALSE else Z=TRUE
1350 BEQ continue ; if bit 6 is mot set then Z=TRUE and drop through to OS_UpdateMEMC
1360 BIC r0,r0,#1<<6 ;clear bit 6 of new data
1370 BIC r1,r1,#1<<6 ;clear bit 6 of mask
1380 B continue ;do OS_UpdateMEMC
1390
1400.continue
1410 LDMFD sp !, {lr}
1420.second_branch
1430 DCD 0
1440.old_branch
1450 DCD 0 ; branch to original SWI decoder
1460.new_branch
1470 DCD 0 ; branch to our new SWI decoder
1480
1490]
1500NEXT pass
1510SYS "OS_File",10,"MEMCPatch",&FFA,,code,P%
1520END
� > MEMCPatSrc
� code &400
( sp = 13
2 lr = 14
< pc = 15
F
P Service_Reset = &27
Z V_FLAG = 1<<28
d
n� pass=0 � 3 � 3
x P%=code
�
[OPT pass
�.module_base
� DCD 0
�, DCD initialise - module_base
�* DCD finalise - module_base
�) DCD service - module_base
�. DCD title_string - module_base
�- DCD help_string - module_base
�, DCD help_table - module_base
�
�o; ---------------------------------------------------------------------------------------------------------
�
�.initialise
STMFD sp !, {lr}
$ BL claim_swi_vector
LDMFD sp !, {pc}
"
,o; ---------------------------------------------------------------------------------------------------------
6
@
.finalise
J STMFD sp !, {lr}
T& BL release_swi_vector
^ LDMFD sp !, {pc}
h
ro; ---------------------------------------------------------------------------------------------------------
|
� .service
�& CMP r1, #Service_Reset
� MOVNES pc, lr
�# STMFD sp !,{r0-r5,lr}
�$ BL claim_swi_vector
�$ LDMFD sp !,{r0-r5,pc}^
�
�o; ---------------------------------------------------------------------------------------------------------
�
�.title_string
�& EQUS "MEMCPatch":DCB 0
�
�.help_string
J EQUS "MEMC Patch":EQUB 9::EQUS "1.01 (27 Nov 1993)":EQUB 0
.help_table
EQUS "PatchingMEMC"
& EQUB 0:ALIGN
0 EQUD 0
: EQUD 0
D EQUD 0
N( EQUD help_text - module_base
X.help_text
b^ EQUS "The MEMC Patch module prevents the setting of bit 6 of the MEMC":EQUB 13
lS EQUS "control register which otherwise crashes the machine.":EQUB 0
v ALIGN
�
�o; ---------------------------------------------------------------------------------------------------------
�
�.release_swi_vector
� MOV r0, #8
� LDR r1, [r0]
�e LDR r2, new_branch ; check that our SWI decoder hasn't been replaced
� CMP r1, r2
�[ LDREQ r1, old_branch ; replace original decoder if it hasn't
� STREQ r1, [r0]
� �Q r0, #0
�" STREQ r1, old_branch
� �QS pc, lr
h LDR r2, old_branch ; if the old branch is already there then do nothing
CMP r1, r2
�QS pc, lr
*
4O ADR r0, error_block ; otherwise return an error
> �RS pc, lr, #V_FLAG
H
R!.error_block DCD &103
\= EQUS "Can't detach SWI handler":DCB 0
f ALIGN
p
zo; ---------------------------------------------------------------------------------------------------------
�
�.claim_swi_vector
� MOV r0, #8
�O LDR r0, [r0] ; get branch to SWI handler
�" STR r0, old_branch
�
�L ADR r1, second_branch-8 ; insert in our own code
�& SUB r0, r0, r1, LSR #2
�
�l BIC r0, r0, #&FF000000 ; handle SUB overflow for when old branch < replacement.
�% �R r0, r0, #&EA000000
�
�% STR r0, second_branch
= ADD r0, r0, #(second_branch-first_branch) / 4
& SUB r0, r0, #&D0000000
$F STR r0, first_branch ; convert to a BNE
.
8 MOV r1, #8
B% ADR r0, swi_patch-8-8
L" MOV r0, r0, LSR #2
V& ADD r0, r0, #&EA000000
` STR r0, [r1]
jQ STR r0, new_branch ; put in a branch to our code
t
~ MOVS pc, lr
�
�o; ---------------------------------------------------------------------------------------------------------
�
�.swi_patch
� STMFD sp !,{lr}
�& BIC lr, lr, #&FC000003
�I LDR lr, [lr,#-4] ; get SWI instruction
�
�& BIC lr, lr, #&FF000000
�# BIC lr, lr, #&20000
�
�K CMP lr, #&1A ; is it OS_UpdateMEMC ?
[ LDMNEFD sp !, {lr} ; otherwise drop through to SWI handler
.first_branch
DCD 0
(a �S lr, r0, #1<<6 ; is bit 6 of new data set ? If so Z=� else Z=�
2t BEQ continue ; if bit 6 is not set then Z=� and drop through to OS_UpdateMEMC
<] �S lr, r1, #1<<6 ; is bit 6 of mask set ? If so Z=� else Z=�
Ft BEQ continue ; if bit 6 is mot set then Z=� and drop through to OS_UpdateMEMC
PL BIC r0,r0,#1<<6 ;clear bit 6 of new data
ZH BIC r1,r1,#1<<6 ;clear bit 6 of mask
dE B continue ;do OS_UpdateMEMC
n
x
.continue
� LDMFD sp !, {lr}
�.second_branch
� DCD 0
�.old_branch
�T DCD 0 ; branch to original SWI decoder
�.new_branch
�S DCD 0 ; branch to our new SWI decoder
�
�]
�
� pass
�-ș "OS_File",10,"MEMCPatch",&FFA,,code,P%
��
� 00000000 0d 00 0a 12 f4 20 3e 20 4d 45 4d 43 50 61 74 53 |..... > MEMCPatS|
00000010 72 63 0d 00 14 0f de 20 63 6f 64 65 20 26 34 30 |rc..... code &40|
00000020 30 0d 00 1e 04 0d 00 28 0b 73 70 20 3d 20 31 33 |0......(.sp = 13|
00000030 0d 00 32 0b 6c 72 20 3d 20 31 34 0d 00 3c 0b 70 |..2.lr = 14..<.p|
00000040 63 20 3d 20 31 35 0d 00 46 04 0d 00 50 1d 53 65 |c = 15..F...P.Se|
00000050 72 76 69 63 65 5f 52 65 73 65 74 20 20 20 3d 20 |rvice_Reset = |
00000060 20 20 20 20 26 32 37 0d 00 5a 1f 56 5f 46 4c 41 | &27..Z.V_FLA|
00000070 47 20 20 20 20 20 20 20 20 20 20 3d 20 20 20 20 |G = |
00000080 20 31 3c 3c 32 38 0d 00 64 04 0d 00 6e 14 e3 20 | 1<<28..d...n.. |
00000090 70 61 73 73 3d 30 20 b8 20 33 20 88 20 33 0d 00 |pass=0 . 3 . 3..|
000000a0 78 0b 50 25 3d 63 6f 64 65 0d 00 82 0d 5b 4f 50 |x.P%=code....[OP|
000000b0 54 20 70 61 73 73 0d 00 8c 10 2e 6d 6f 64 75 6c |T pass.....modul|
000000c0 65 5f 62 61 73 65 0d 00 96 15 20 20 20 20 20 20 |e_base.... |
000000d0 20 20 44 43 44 20 20 20 20 20 30 0d 00 a0 2c 20 | DCD 0..., |
000000e0 20 20 20 20 20 20 20 44 43 44 20 20 20 20 20 69 | DCD i|
000000f0 6e 69 74 69 61 6c 69 73 65 20 2d 20 6d 6f 64 75 |nitialise - modu|
00000100 6c 65 5f 62 61 73 65 0d 00 aa 2a 20 20 20 20 20 |le_base...* |
00000110 20 20 20 44 43 44 20 20 20 20 20 66 69 6e 61 6c | DCD final|
00000120 69 73 65 20 2d 20 6d 6f 64 75 6c 65 5f 62 61 73 |ise - module_bas|
00000130 65 0d 00 b4 29 20 20 20 20 20 20 20 20 44 43 44 |e...) DCD|
00000140 20 20 20 20 20 73 65 72 76 69 63 65 20 2d 20 6d | service - m|
00000150 6f 64 75 6c 65 5f 62 61 73 65 0d 00 be 2e 20 20 |odule_base.... |
00000160 20 20 20 20 20 20 44 43 44 20 20 20 20 20 74 69 | DCD ti|
00000170 74 6c 65 5f 73 74 72 69 6e 67 20 2d 20 6d 6f 64 |tle_string - mod|
00000180 75 6c 65 5f 62 61 73 65 0d 00 c8 2d 20 20 20 20 |ule_base...- |
00000190 20 20 20 20 44 43 44 20 20 20 20 20 68 65 6c 70 | DCD help|
000001a0 5f 73 74 72 69 6e 67 20 2d 20 6d 6f 64 75 6c 65 |_string - module|
000001b0 5f 62 61 73 65 0d 00 d2 2c 20 20 20 20 20 20 20 |_base..., |
000001c0 20 44 43 44 20 20 20 20 20 68 65 6c 70 5f 74 61 | DCD help_ta|
000001d0 62 6c 65 20 2d 20 6d 6f 64 75 6c 65 5f 62 61 73 |ble - module_bas|
000001e0 65 0d 00 dc 04 0d 00 e6 6f 3b 20 2d 2d 2d 2d 2d |e.......o; -----|
000001f0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |----------------|
*
00000250 2d 2d 2d 2d 0d 00 f0 04 0d 00 fa 0f 2e 69 6e 69 |----.........ini|
00000260 74 69 61 6c 69 73 65 0d 01 04 1e 20 20 20 20 20 |tialise.... |
00000270 20 20 20 53 54 4d 46 44 20 20 20 73 70 20 21 2c | STMFD sp !,|
00000280 20 7b 6c 72 7d 0d 01 0e 24 20 20 20 20 20 20 20 | {lr}...$ |
00000290 20 42 4c 20 20 20 20 20 20 63 6c 61 69 6d 5f 73 | BL claim_s|
000002a0 77 69 5f 76 65 63 74 6f 72 0d 01 18 1e 20 20 20 |wi_vector.... |
000002b0 20 20 20 20 20 4c 44 4d 46 44 20 20 20 73 70 20 | LDMFD sp |
000002c0 21 2c 20 7b 70 63 7d 0d 01 22 04 0d 01 2c 6f 3b |!, {pc}.."...,o;|
000002d0 20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d | ---------------|
000002e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |----------------|
*
00000330 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 0d 01 36 04 0d 01 |----------..6...|
00000340 40 0d 2e 66 69 6e 61 6c 69 73 65 0d 01 4a 1e 20 |@..finalise..J. |
00000350 20 20 20 20 20 20 20 53 54 4d 46 44 20 20 20 73 | STMFD s|
00000360 70 20 21 2c 20 7b 6c 72 7d 0d 01 54 26 20 20 20 |p !, {lr}..T& |
00000370 20 20 20 20 20 42 4c 20 20 20 20 20 20 72 65 6c | BL rel|
00000380 65 61 73 65 5f 73 77 69 5f 76 65 63 74 6f 72 0d |ease_swi_vector.|
00000390 01 5e 1e 20 20 20 20 20 20 20 20 4c 44 4d 46 44 |.^. LDMFD|
000003a0 20 20 20 73 70 20 21 2c 20 7b 70 63 7d 0d 01 68 | sp !, {pc}..h|
000003b0 04 0d 01 72 6f 3b 20 2d 2d 2d 2d 2d 2d 2d 2d 2d |...ro; ---------|
000003c0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |----------------|
*
00000420 0d 01 7c 04 0d 01 86 0c 2e 73 65 72 76 69 63 65 |..|......service|
00000430 0d 01 90 26 20 20 20 20 20 20 20 20 43 4d 50 20 |...& CMP |
00000440 20 20 20 20 72 31 2c 20 23 53 65 72 76 69 63 65 | r1, #Service|
00000450 5f 52 65 73 65 74 0d 01 9a 1a 20 20 20 20 20 20 |_Reset.... |
00000460 20 20 4d 4f 56 4e 45 53 20 20 70 63 2c 20 6c 72 | MOVNES pc, lr|
00000470 0d 01 a4 23 20 20 20 20 20 20 20 20 53 54 4d 46 |...# STMF|
00000480 44 20 20 20 73 70 20 21 2c 7b 72 30 2d 72 35 2c |D sp !,{r0-r5,|
00000490 6c 72 7d 0d 01 ae 24 20 20 20 20 20 20 20 20 42 |lr}...$ B|
000004a0 4c 20 20 20 20 20 20 63 6c 61 69 6d 5f 73 77 69 |L claim_swi|
000004b0 5f 76 65 63 74 6f 72 0d 01 b8 24 20 20 20 20 20 |_vector...$ |
000004c0 20 20 20 4c 44 4d 46 44 20 20 20 73 70 20 21 2c | LDMFD sp !,|
000004d0 7b 72 30 2d 72 35 2c 70 63 7d 5e 0d 01 c2 04 0d |{r0-r5,pc}^.....|
000004e0 01 cc 6f 3b 20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |..o; -----------|
000004f0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |----------------|
*
00000540 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 0d 01 |--------------..|
00000550 d6 04 0d 01 e0 11 2e 74 69 74 6c 65 5f 73 74 72 |.......title_str|
00000560 69 6e 67 0d 01 ea 26 20 20 20 20 20 20 20 20 45 |ing...& E|
00000570 51 55 53 20 20 20 20 20 22 4d 45 4d 43 50 61 74 |QUS "MEMCPat|
00000580 63 68 22 3a 44 43 42 20 30 0d 01 f4 04 0d 01 fe |ch":DCB 0.......|
00000590 10 2e 68 65 6c 70 5f 73 74 72 69 6e 67 0d 02 08 |..help_string...|
000005a0 4a 20 20 20 20 20 20 20 20 45 51 55 53 20 20 20 |J EQUS |
000005b0 20 20 22 4d 45 4d 43 20 50 61 74 63 68 22 3a 45 | "MEMC Patch":E|
000005c0 51 55 42 20 39 3a 3a 45 51 55 53 20 22 31 2e 30 |QUB 9::EQUS "1.0|
000005d0 31 20 28 32 37 20 4e 6f 76 20 31 39 39 33 29 22 |1 (27 Nov 1993)"|
000005e0 3a 45 51 55 42 20 30 0d 02 12 0f 2e 68 65 6c 70 |:EQUB 0.....help|
000005f0 5f 74 61 62 6c 65 0d 02 1c 1f 20 20 20 20 20 20 |_table.... |
00000600 20 20 45 51 55 53 20 22 50 61 74 63 68 69 6e 67 | EQUS "Patching|
00000610 4d 45 4d 43 22 0d 02 26 18 20 20 20 20 20 20 20 |MEMC"..&. |
00000620 20 45 51 55 42 20 30 3a 41 4c 49 47 4e 0d 02 30 | EQUB 0:ALIGN..0|
00000630 12 20 20 20 20 20 20 20 20 45 51 55 44 20 30 0d |. EQUD 0.|
00000640 02 3a 12 20 20 20 20 20 20 20 20 45 51 55 44 20 |.:. EQUD |
00000650 30 0d 02 44 12 20 20 20 20 20 20 20 20 45 51 55 |0..D. EQU|
00000660 44 20 30 0d 02 4e 28 20 20 20 20 20 20 20 20 45 |D 0..N( E|
00000670 51 55 44 20 68 65 6c 70 5f 74 65 78 74 20 2d 20 |QUD help_text - |
00000680 6d 6f 64 75 6c 65 5f 62 61 73 65 0d 02 58 0e 2e |module_base..X..|
00000690 68 65 6c 70 5f 74 65 78 74 0d 02 62 5e 20 20 20 |help_text..b^ |
000006a0 20 20 20 20 20 45 51 55 53 20 20 20 20 20 22 54 | EQUS "T|
000006b0 68 65 20 4d 45 4d 43 20 50 61 74 63 68 20 6d 6f |he MEMC Patch mo|
000006c0 64 75 6c 65 20 70 72 65 76 65 6e 74 73 20 74 68 |dule prevents th|
000006d0 65 20 73 65 74 74 69 6e 67 20 6f 66 20 62 69 74 |e setting of bit|
000006e0 20 36 20 6f 66 20 74 68 65 20 4d 45 4d 43 22 3a | 6 of the MEMC":|
000006f0 45 51 55 42 20 31 33 0d 02 6c 53 20 20 20 20 20 |EQUB 13..lS |
00000700 20 20 20 45 51 55 53 20 20 20 20 20 22 63 6f 6e | EQUS "con|
00000710 74 72 6f 6c 20 72 65 67 69 73 74 65 72 20 77 68 |trol register wh|
00000720 69 63 68 20 6f 74 68 65 72 77 69 73 65 20 63 72 |ich otherwise cr|
00000730 61 73 68 65 73 20 74 68 65 20 6d 61 63 68 69 6e |ashes the machin|
00000740 65 2e 22 3a 45 51 55 42 20 30 0d 02 76 11 20 20 |e.":EQUB 0..v. |
00000750 20 20 20 20 20 20 41 4c 49 47 4e 0d 02 80 04 0d | ALIGN.....|
00000760 02 8a 6f 3b 20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |..o; -----------|
00000770 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |----------------|
*
000007c0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 0d 02 |--------------..|
000007d0 94 04 0d 02 9e 17 2e 72 65 6c 65 61 73 65 5f 73 |.......release_s|
000007e0 77 69 5f 76 65 63 74 6f 72 0d 02 a8 1a 20 20 20 |wi_vector.... |
000007f0 20 20 20 20 20 4d 4f 56 20 20 20 20 20 72 30 2c | MOV r0,|
00000800 20 23 38 0d 02 b2 1c 20 20 20 20 20 20 20 20 4c | #8.... L|
00000810 44 52 20 20 20 20 20 72 31 2c 20 5b 72 30 5d 0d |DR r1, [r0].|
00000820 02 bc 65 20 20 20 20 20 20 20 20 4c 44 52 20 20 |..e LDR |
00000830 20 20 20 72 32 2c 20 6e 65 77 5f 62 72 61 6e 63 | r2, new_branc|
00000840 68 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 |h |
00000850 20 20 20 3b 20 63 68 65 63 6b 20 74 68 61 74 20 | ; check that |
00000860 6f 75 72 20 53 57 49 20 64 65 63 6f 64 65 72 20 |our SWI decoder |
00000870 68 61 73 6e 27 74 20 62 65 65 6e 20 72 65 70 6c |hasn't been repl|
00000880 61 63 65 64 0d 02 c6 1a 20 20 20 20 20 20 20 20 |aced.... |
00000890 43 4d 50 20 20 20 20 20 72 31 2c 20 72 32 0d 02 |CMP r1, r2..|
000008a0 d0 5b 20 20 20 20 20 20 20 20 4c 44 52 45 51 20 |.[ LDREQ |
000008b0 20 20 72 31 2c 20 6f 6c 64 5f 62 72 61 6e 63 68 | r1, old_branch|
000008c0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | |
000008d0 20 20 3b 20 72 65 70 6c 61 63 65 20 6f 72 69 67 | ; replace orig|
000008e0 69 6e 61 6c 20 64 65 63 6f 64 65 72 20 69 66 20 |inal decoder if |
000008f0 69 74 20 68 61 73 6e 27 74 0d 02 da 1c 20 20 20 |it hasn't.... |
00000900 20 20 20 20 20 53 54 52 45 51 20 20 20 72 31 2c | STREQ r1,|
00000910 20 5b 72 30 5d 0d 02 e4 17 20 20 20 20 20 20 20 | [r0].... |
00000920 20 ec 51 20 20 20 72 30 2c 20 23 30 0d 02 ee 22 | .Q r0, #0..."|
00000930 20 20 20 20 20 20 20 20 53 54 52 45 51 20 20 20 | STREQ |
00000940 72 31 2c 20 6f 6c 64 5f 62 72 61 6e 63 68 0d 02 |r1, old_branch..|
00000950 f8 17 20 20 20 20 20 20 20 20 ec 51 53 20 20 70 |.. .QS p|
00000960 63 2c 20 6c 72 0d 03 02 04 0d 03 0c 68 20 20 20 |c, lr.......h |
00000970 20 20 20 20 20 4c 44 52 20 20 20 20 20 72 32 2c | LDR r2,|
00000980 20 6f 6c 64 5f 62 72 61 6e 63 68 20 20 20 20 20 | old_branch |
00000990 20 20 20 20 20 20 20 20 20 20 20 20 20 3b 20 69 | ; i|
000009a0 66 20 74 68 65 20 6f 6c 64 20 62 72 61 6e 63 68 |f the old branch|
000009b0 20 69 73 20 61 6c 72 65 61 64 79 20 74 68 65 72 | is already ther|
000009c0 65 20 74 68 65 6e 20 64 6f 20 6e 6f 74 68 69 6e |e then do nothin|
000009d0 67 0d 03 16 1a 20 20 20 20 20 20 20 20 43 4d 50 |g.... CMP|
000009e0 20 20 20 20 20 72 31 2c 20 72 32 0d 03 20 17 20 | r1, r2.. . |
000009f0 20 20 20 20 20 20 20 ec 51 53 20 20 70 63 2c 20 | .QS pc, |
00000a00 6c 72 0d 03 2a 04 0d 03 34 4f 20 20 20 20 20 20 |lr..*...4O |
00000a10 20 20 41 44 52 20 20 20 72 30 2c 20 65 72 72 6f | ADR r0, erro|
00000a20 72 5f 62 6c 6f 63 6b 20 20 20 20 20 20 20 20 20 |r_block |
00000a30 20 20 20 20 20 20 20 20 20 20 3b 20 6f 74 68 65 | ; othe|
00000a40 72 77 69 73 65 20 72 65 74 75 72 6e 20 61 6e 20 |rwise return an |
00000a50 65 72 72 6f 72 0d 03 3e 20 20 20 20 20 20 20 20 |error..> |
00000a60 20 84 52 53 20 20 70 63 2c 20 6c 72 2c 20 23 56 | .RS pc, lr, #V|
00000a70 5f 46 4c 41 47 0d 03 48 04 0d 03 52 21 2e 65 72 |_FLAG..H...R!.er|
00000a80 72 6f 72 5f 62 6c 6f 63 6b 20 20 20 20 20 44 43 |ror_block DC|
00000a90 44 20 20 20 20 20 26 31 30 33 0d 03 5c 3d 20 20 |D &103..\= |
00000aa0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 45 51 | EQ|
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00000ad0 22 3a 44 43 42 20 30 0d 03 66 19 20 20 20 20 20 |":DCB 0..f. |
00000ae0 20 20 20 20 20 20 20 20 20 20 20 41 4c 49 47 4e | ALIGN|
00000af0 0d 03 70 04 0d 03 7a 6f 3b 20 2d 2d 2d 2d 2d 2d |..p...zo; ------|
00000b00 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |----------------|
*
00000b60 2d 2d 2d 0d 03 84 04 0d 03 8e 15 2e 63 6c 61 69 |---.........clai|
00000b70 6d 5f 73 77 69 5f 76 65 63 74 6f 72 0d 03 98 1a |m_swi_vector....|
00000b80 20 20 20 20 20 20 20 20 4d 4f 56 20 20 20 20 20 | MOV |
00000b90 72 30 2c 20 23 38 0d 03 a2 4f 20 20 20 20 20 20 |r0, #8...O |
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00000bb0 30 5d 20 20 20 20 20 20 20 20 20 20 20 20 20 20 |0] |
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00000bd0 62 72 61 6e 63 68 20 74 6f 20 53 57 49 20 68 61 |branch to SWI ha|
00000be0 6e 64 6c 65 72 0d 03 ac 22 20 20 20 20 20 20 20 |ndler..." |
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00000c00 5f 62 72 61 6e 63 68 0d 03 b6 04 0d 03 c0 4c 20 |_branch.......L |
00000c10 20 20 20 20 20 20 20 41 44 52 20 20 20 20 20 72 | ADR r|
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00000c30 2d 38 20 20 20 20 20 20 20 20 20 20 20 20 20 3b |-8 ;|
00000c40 20 69 6e 73 65 72 74 20 69 6e 20 6f 75 72 20 6f | insert in our o|
00000c50 77 6e 20 63 6f 64 65 0d 03 ca 26 20 20 20 20 20 |wn code...& |
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00000c80 04 0d 03 de 6c 20 20 20 20 20 20 20 20 42 49 43 |....l BIC|
00000c90 20 20 20 20 20 72 30 2c 20 72 30 2c 20 23 26 46 | r0, r0, #&F|
00000ca0 46 30 30 30 30 30 30 20 20 20 20 20 20 20 20 20 |F000000 |
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00000cc0 42 20 6f 76 65 72 66 6c 6f 77 20 66 6f 72 20 77 |B overflow for w|
00000cd0 68 65 6e 20 6f 6c 64 20 62 72 61 6e 63 68 20 3c |hen old branch <|
00000ce0 20 72 65 70 6c 61 63 65 6d 65 6e 74 2e 0d 03 e8 | replacement....|
00000cf0 25 20 20 20 20 20 20 20 20 84 52 20 20 20 20 20 |% .R |
00000d00 72 30 2c 20 72 30 2c 20 23 26 45 41 30 30 30 30 |r0, r0, #&EA0000|
00000d10 30 30 0d 03 f2 04 0d 03 fc 25 20 20 20 20 20 20 |00.......% |
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00000d30 63 6f 6e 64 5f 62 72 61 6e 63 68 0d 04 06 04 0d |cond_branch.....|
00000d40 04 10 3d 20 20 20 20 20 20 20 20 41 44 44 20 20 |..= ADD |
00000d50 20 20 20 72 30 2c 20 72 30 2c 20 23 28 73 65 63 | r0, r0, #(sec|
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00000d70 5f 62 72 61 6e 63 68 29 20 2f 20 34 0d 04 1a 26 |_branch) / 4...&|
00000d80 20 20 20 20 20 20 20 20 53 55 42 20 20 20 20 20 | SUB |
00000d90 72 30 2c 20 72 30 2c 20 23 26 44 30 30 30 30 30 |r0, r0, #&D00000|
00000da0 30 30 0d 04 24 46 20 20 20 20 20 20 20 20 53 54 |00..$F ST|
00000db0 52 20 20 20 20 20 72 30 2c 20 66 69 72 73 74 5f |R r0, first_|
00000dc0 62 72 61 6e 63 68 20 20 20 20 20 20 20 20 20 20 |branch |
00000dd0 20 20 20 20 20 20 3b 20 63 6f 6e 76 65 72 74 20 | ; convert |
00000de0 74 6f 20 61 20 42 4e 45 0d 04 2e 04 0d 04 38 1a |to a BNE......8.|
00000df0 20 20 20 20 20 20 20 20 4d 4f 56 20 20 20 20 20 | MOV |
00000e00 72 31 2c 20 23 38 0d 04 42 25 20 20 20 20 20 20 |r1, #8..B% |
00000e10 20 20 41 44 52 20 20 20 20 20 72 30 2c 20 73 77 | ADR r0, sw|
00000e20 69 5f 70 61 74 63 68 2d 38 2d 38 0d 04 4c 22 20 |i_patch-8-8..L" |
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00000e50 26 20 20 20 20 20 20 20 20 41 44 44 20 20 20 20 |& ADD |
00000e60 20 72 30 2c 20 72 30 2c 20 23 26 45 41 30 30 30 | r0, r0, #&EA000|
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00000ea0 20 20 20 72 30 2c 20 6e 65 77 5f 62 72 61 6e 63 | r0, new_branc|
00000eb0 68 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 |h |
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00000ee0 0d 04 74 04 0d 04 7e 1b 20 20 20 20 20 20 20 20 |..t...~. |
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00000f00 04 88 04 0d 04 92 6f 3b 20 2d 2d 2d 2d 2d 2d 2d |......o; -------|
00000f10 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |----------------|
*
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00000f80 61 74 63 68 0d 04 b0 1d 20 20 20 20 20 20 20 20 |atch.... |
00000f90 53 54 4d 46 44 20 20 20 73 70 20 21 2c 7b 6c 72 |STMFD sp !,{lr|
00000fa0 7d 0d 04 ba 26 20 20 20 20 20 20 20 20 42 49 43 |}...& BIC|
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00001010 0d 04 ce 04 0d 04 d8 26 20 20 20 20 20 20 20 20 |.......& |
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00001030 23 26 46 46 30 30 30 30 30 30 0d 04 e2 23 20 20 |#&FF000000...# |
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00001080 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | |
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00001150 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | |
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00001260 5a 3d b9 0d 05 46 74 20 20 20 20 20 20 20 20 42 |Z=...Ft B|
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00001280 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | |
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00001370 20 20 20 20 20 20 20 42 20 63 6f 6e 74 69 6e 75 | B continu|
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000013f0 68 0d 05 96 15 20 20 20 20 20 20 20 20 44 43 44 |h.... DCD|
00001400 20 20 20 20 20 30 0d 05 a0 0f 2e 6f 6c 64 5f 62 | 0.....old_b|
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00001420 20 44 43 44 20 20 20 20 20 30 20 20 20 20 20 20 | DCD 0 |
00001430 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | |
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00001490 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | |
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00001500 46 41 2c 2c 63 6f 64 65 2c 50 25 0d 05 f0 05 e0 |FA,,code,P%.....|
00001510 0d ff |..|
00001512 
.