Home » Recent acquisitions » Acorn ADFS disks » adfs_AcornUser_199611.adf » Extras » Harrison/PrcsVector/SWIdetails
Harrison/PrcsVector/SWIdetails
This website contains an archive of files for the Acorn Electron, BBC Micro, Acorn Archimedes, Commodore 16 and Commodore 64 computers, which Dominic Ford has rescued from his private collection of floppy disks and cassettes.
Some of these files were originally commercial releases in the 1980s and 1990s, but they are now widely available online. I assume that copyright over them is no longer being asserted. If you own the copyright and would like files to be removed, please contact me.
| Tape/disk: | Home » Recent acquisitions » Acorn ADFS disks » adfs_AcornUser_199611.adf » Extras |
| Filename: | Harrison/PrcsVector/SWIdetails |
| Read OK: | ✔ |
| File size: | 07C5 bytes |
| Load address: | 0000 |
| Exec address: | 0000 |
File contents
SYS "OS_ClaimProcessorVector" &00069
-----------------------------------------------------------------------------
On Entry:
R0 = vector number & flags
R1 = replacement value
If releasing vector R2 = current address expected on vector
On Exit:
R0 & R2 preserved
R1 = old value, if vector claimed
Interrupts:
IRQs unaffected, FIRQs enabled
V flag set if current expected address, R2, is not the owner of the vector
when releasing.
This SWI replaces one of the processor hardware vectors. The replacement code
should either replace it's vectors' code completely or it should pass on the
call to the previous owner after examining it, if it cannot cope. For the
second case, the address of the previous owner can be found in R1 after
claiming the vector, but the program should claim the vector with interrupts
off so that the vector will not be called between the claim and the reading
of the previous owner.
The format of R0 on entry is as follows:
bits 0-7 = vector number, see below
bit 8 = 1 to claim vector, 0 to release
bits 9-31 = reserved, should be 0
Possible vector numbers are as follows
0 - Branch through zero
1 - Undefined instruction type
2 - Software interrupt (SWI)
3 - Abort (prefetch)
4 - Abort (data)
5 - Address exception (Arm2 & Arm3 only)
Note: all vectors *except* the SWI vector (number 2) and the undefined
instruction vector (number 1), are reset to their defaults by the operating
system whenever any task ends. This cannot be avoided on pre-RiscOS 3.5
computers, but it should not be relied upon, and any claimed vectors should
be restored by the claiming program when it exits.
This information can be found on page 46, volume 5 of the RiscOS 3 PRMs.
Furthur information on the action taken by each vector on Arm2 and Arm3
machines can be found on page 3-14, 'ARM Family Data Manual', Prentice-Hall
1990. 00000000 53 59 53 20 22 4f 53 5f 43 6c 61 69 6d 50 72 6f |SYS "OS_ClaimPro| 00000010 63 65 73 73 6f 72 56 65 63 74 6f 72 22 20 20 20 |cessorVector" | 00000020 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | * 00000040 20 20 20 20 20 20 20 26 30 30 30 36 39 0a 2d 2d | &00069.--| 00000050 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |----------------| * 00000090 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 0a 0a 4f 6e 20 |-----------..On | 000000a0 45 6e 74 72 79 3a 0a 0a 20 20 20 20 20 20 20 20 |Entry:.. | 000000b0 52 30 20 3d 20 76 65 63 74 6f 72 20 6e 75 6d 62 |R0 = vector numb| 000000c0 65 72 20 26 20 66 6c 61 67 73 0a 20 20 20 20 20 |er & flags. | 000000d0 20 20 20 52 31 20 3d 20 72 65 70 6c 61 63 65 6d | R1 = replacem| 000000e0 65 6e 74 20 76 61 6c 75 65 0a 20 20 20 20 20 20 |ent value. | 000000f0 20 20 0a 20 20 20 20 20 20 20 20 49 66 20 72 65 | . If re| 00000100 6c 65 61 73 69 6e 67 20 76 65 63 74 6f 72 20 52 |leasing vector R| 00000110 32 20 3d 20 63 75 72 72 65 6e 74 20 61 64 64 72 |2 = current addr| 00000120 65 73 73 20 65 78 70 65 63 74 65 64 20 6f 6e 20 |ess expected on | 00000130 76 65 63 74 6f 72 0a 0a 4f 6e 20 45 78 69 74 3a |vector..On Exit:| 00000140 0a 0a 20 20 20 20 20 20 20 20 52 30 20 26 20 52 |.. R0 & R| 00000150 32 20 70 72 65 73 65 72 76 65 64 0a 20 20 20 20 |2 preserved. | 00000160 20 20 20 20 52 31 20 3d 20 6f 6c 64 20 76 61 6c | R1 = old val| 00000170 75 65 2c 20 69 66 20 76 65 63 74 6f 72 20 63 6c |ue, if vector cl| 00000180 61 69 6d 65 64 0a 0a 49 6e 74 65 72 72 75 70 74 |aimed..Interrupt| 00000190 73 3a 0a 0a 20 20 20 20 20 20 20 20 49 52 51 73 |s:.. IRQs| 000001a0 20 75 6e 61 66 66 65 63 74 65 64 2c 20 46 49 52 | unaffected, FIR| 000001b0 51 73 20 65 6e 61 62 6c 65 64 0a 0a 56 20 66 6c |Qs enabled..V fl| 000001c0 61 67 20 73 65 74 20 69 66 20 63 75 72 72 65 6e |ag set if curren| 000001d0 74 20 65 78 70 65 63 74 65 64 20 61 64 64 72 65 |t expected addre| 000001e0 73 73 2c 20 52 32 2c 20 69 73 20 6e 6f 74 20 74 |ss, R2, is not t| 000001f0 68 65 20 6f 77 6e 65 72 20 6f 66 20 74 68 65 20 |he owner of the | 00000200 76 65 63 74 6f 72 0a 77 68 65 6e 20 72 65 6c 65 |vector.when rele| 00000210 61 73 69 6e 67 2e 0a 0a 0a 54 68 69 73 20 53 57 |asing....This SW| 00000220 49 20 72 65 70 6c 61 63 65 73 20 6f 6e 65 20 6f |I replaces one o| 00000230 66 20 74 68 65 20 70 72 6f 63 65 73 73 6f 72 20 |f the processor | 00000240 68 61 72 64 77 61 72 65 20 76 65 63 74 6f 72 73 |hardware vectors| 00000250 2e 20 54 68 65 20 72 65 70 6c 61 63 65 6d 65 6e |. The replacemen| 00000260 74 20 63 6f 64 65 0a 73 68 6f 75 6c 64 20 65 69 |t code.should ei| 00000270 74 68 65 72 20 72 65 70 6c 61 63 65 20 69 74 27 |ther replace it'| 00000280 73 20 76 65 63 74 6f 72 73 27 20 63 6f 64 65 20 |s vectors' code | 00000290 63 6f 6d 70 6c 65 74 65 6c 79 20 6f 72 20 69 74 |completely or it| 000002a0 20 73 68 6f 75 6c 64 20 70 61 73 73 20 6f 6e 20 | should pass on | 000002b0 74 68 65 0a 63 61 6c 6c 20 74 6f 20 74 68 65 20 |the.call to the | 000002c0 70 72 65 76 69 6f 75 73 20 6f 77 6e 65 72 20 61 |previous owner a| 000002d0 66 74 65 72 20 65 78 61 6d 69 6e 69 6e 67 20 69 |fter examining i| 000002e0 74 2c 20 69 66 20 69 74 20 63 61 6e 6e 6f 74 20 |t, if it cannot | 000002f0 63 6f 70 65 2e 20 46 6f 72 20 74 68 65 0a 73 65 |cope. For the.se| 00000300 63 6f 6e 64 20 63 61 73 65 2c 20 74 68 65 20 61 |cond case, the a| 00000310 64 64 72 65 73 73 20 6f 66 20 74 68 65 20 70 72 |ddress of the pr| 00000320 65 76 69 6f 75 73 20 6f 77 6e 65 72 20 63 61 6e |evious owner can| 00000330 20 62 65 20 66 6f 75 6e 64 20 69 6e 20 52 31 20 | be found in R1 | 00000340 61 66 74 65 72 0a 63 6c 61 69 6d 69 6e 67 20 74 |after.claiming t| 00000350 68 65 20 76 65 63 74 6f 72 2c 20 62 75 74 20 74 |he vector, but t| 00000360 68 65 20 70 72 6f 67 72 61 6d 20 73 68 6f 75 6c |he program shoul| 00000370 64 20 63 6c 61 69 6d 20 74 68 65 20 76 65 63 74 |d claim the vect| 00000380 6f 72 20 77 69 74 68 20 69 6e 74 65 72 72 75 70 |or with interrup| 00000390 74 73 0a 6f 66 66 20 73 6f 20 74 68 61 74 20 74 |ts.off so that t| 000003a0 68 65 20 76 65 63 74 6f 72 20 77 69 6c 6c 20 6e |he vector will n| 000003b0 6f 74 20 62 65 20 63 61 6c 6c 65 64 20 62 65 74 |ot be called bet| 000003c0 77 65 65 6e 20 74 68 65 20 63 6c 61 69 6d 20 61 |ween the claim a| 000003d0 6e 64 20 74 68 65 20 72 65 61 64 69 6e 67 0a 6f |nd the reading.o| 000003e0 66 20 74 68 65 20 70 72 65 76 69 6f 75 73 20 6f |f the previous o| 000003f0 77 6e 65 72 2e 0a 0a 54 68 65 20 66 6f 72 6d 61 |wner...The forma| 00000400 74 20 6f 66 20 52 30 20 6f 6e 20 65 6e 74 72 79 |t of R0 on entry| 00000410 20 69 73 20 61 73 20 66 6f 6c 6c 6f 77 73 3a 0a | is as follows:.| 00000420 0a 20 62 69 74 73 20 30 2d 37 20 20 3d 20 76 65 |. bits 0-7 = ve| 00000430 63 74 6f 72 20 6e 75 6d 62 65 72 2c 20 73 65 65 |ctor number, see| 00000440 20 62 65 6c 6f 77 0a 20 62 69 74 20 20 38 20 20 | below. bit 8 | 00000450 20 20 3d 20 31 20 74 6f 20 63 6c 61 69 6d 20 76 | = 1 to claim v| 00000460 65 63 74 6f 72 2c 20 30 20 74 6f 20 72 65 6c 65 |ector, 0 to rele| 00000470 61 73 65 0a 20 62 69 74 73 20 39 2d 33 31 20 3d |ase. bits 9-31 =| 00000480 20 72 65 73 65 72 76 65 64 2c 20 73 68 6f 75 6c | reserved, shoul| 00000490 64 20 62 65 20 30 0a 0a 50 6f 73 73 69 62 6c 65 |d be 0..Possible| 000004a0 20 76 65 63 74 6f 72 20 6e 75 6d 62 65 72 73 20 | vector numbers | 000004b0 61 72 65 20 61 73 20 66 6f 6c 6c 6f 77 73 0a 0a |are as follows..| 000004c0 20 20 20 20 20 20 30 20 2d 20 42 72 61 6e 63 68 | 0 - Branch| 000004d0 20 74 68 72 6f 75 67 68 20 7a 65 72 6f 0a 20 20 | through zero. | 000004e0 20 20 20 20 31 20 2d 20 55 6e 64 65 66 69 6e 65 | 1 - Undefine| 000004f0 64 20 69 6e 73 74 72 75 63 74 69 6f 6e 20 74 79 |d instruction ty| 00000500 70 65 0a 20 20 20 20 20 20 32 20 2d 20 53 6f 66 |pe. 2 - Sof| 00000510 74 77 61 72 65 20 69 6e 74 65 72 72 75 70 74 20 |tware interrupt | 00000520 28 53 57 49 29 0a 20 20 20 20 20 20 33 20 2d 20 |(SWI). 3 - | 00000530 41 62 6f 72 74 20 28 70 72 65 66 65 74 63 68 29 |Abort (prefetch)| 00000540 0a 20 20 20 20 20 20 34 20 2d 20 41 62 6f 72 74 |. 4 - Abort| 00000550 20 28 64 61 74 61 29 0a 20 20 20 20 20 20 35 20 | (data). 5 | 00000560 2d 20 41 64 64 72 65 73 73 20 65 78 63 65 70 74 |- Address except| 00000570 69 6f 6e 20 28 41 72 6d 32 20 26 20 41 72 6d 33 |ion (Arm2 & Arm3| 00000580 20 6f 6e 6c 79 29 0a 0a 4e 6f 74 65 3a 20 61 6c | only)..Note: al| 00000590 6c 20 76 65 63 74 6f 72 73 20 2a 65 78 63 65 70 |l vectors *excep| 000005a0 74 2a 20 74 68 65 20 53 57 49 20 76 65 63 74 6f |t* the SWI vecto| 000005b0 72 20 28 6e 75 6d 62 65 72 20 32 29 20 61 6e 64 |r (number 2) and| 000005c0 20 74 68 65 20 75 6e 64 65 66 69 6e 65 64 0a 69 | the undefined.i| 000005d0 6e 73 74 72 75 63 74 69 6f 6e 20 76 65 63 74 6f |nstruction vecto| 000005e0 72 20 28 6e 75 6d 62 65 72 20 31 29 2c 20 61 72 |r (number 1), ar| 000005f0 65 20 72 65 73 65 74 20 74 6f 20 74 68 65 69 72 |e reset to their| 00000600 20 64 65 66 61 75 6c 74 73 20 62 79 20 74 68 65 | defaults by the| 00000610 20 6f 70 65 72 61 74 69 6e 67 0a 73 79 73 74 65 | operating.syste| 00000620 6d 20 77 68 65 6e 65 76 65 72 20 61 6e 79 20 74 |m whenever any t| 00000630 61 73 6b 20 65 6e 64 73 2e 20 54 68 69 73 20 63 |ask ends. This c| 00000640 61 6e 6e 6f 74 20 62 65 20 61 76 6f 69 64 65 64 |annot be avoided| 00000650 20 6f 6e 20 70 72 65 2d 52 69 73 63 4f 53 20 33 | on pre-RiscOS 3| 00000660 2e 35 0a 63 6f 6d 70 75 74 65 72 73 2c 20 62 75 |.5.computers, bu| 00000670 74 20 69 74 20 73 68 6f 75 6c 64 20 6e 6f 74 20 |t it should not | 00000680 62 65 20 72 65 6c 69 65 64 20 75 70 6f 6e 2c 20 |be relied upon, | 00000690 61 6e 64 20 61 6e 79 20 63 6c 61 69 6d 65 64 20 |and any claimed | 000006a0 76 65 63 74 6f 72 73 20 73 68 6f 75 6c 64 0a 62 |vectors should.b| 000006b0 65 20 72 65 73 74 6f 72 65 64 20 62 79 20 74 68 |e restored by th| 000006c0 65 20 63 6c 61 69 6d 69 6e 67 20 70 72 6f 67 72 |e claiming progr| 000006d0 61 6d 20 77 68 65 6e 20 69 74 20 65 78 69 74 73 |am when it exits| 000006e0 2e 0a 0a 54 68 69 73 20 69 6e 66 6f 72 6d 61 74 |...This informat| 000006f0 69 6f 6e 20 63 61 6e 20 62 65 20 66 6f 75 6e 64 |ion can be found| 00000700 20 6f 6e 20 70 61 67 65 20 34 36 2c 20 76 6f 6c | on page 46, vol| 00000710 75 6d 65 20 35 20 6f 66 20 74 68 65 20 52 69 73 |ume 5 of the Ris| 00000720 63 4f 53 20 33 20 50 52 4d 73 2e 0a 46 75 72 74 |cOS 3 PRMs..Furt| 00000730 68 75 72 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 20 |hur information | 00000740 6f 6e 20 74 68 65 20 61 63 74 69 6f 6e 20 74 61 |on the action ta| 00000750 6b 65 6e 20 62 79 20 65 61 63 68 20 76 65 63 74 |ken by each vect| 00000760 6f 72 20 6f 6e 20 41 72 6d 32 20 61 6e 64 20 41 |or on Arm2 and A| 00000770 72 6d 33 0a 6d 61 63 68 69 6e 65 73 20 63 61 6e |rm3.machines can| 00000780 20 62 65 20 66 6f 75 6e 64 20 6f 6e 20 70 61 67 | be found on pag| 00000790 65 20 33 2d 31 34 2c 20 27 41 52 4d 20 46 61 6d |e 3-14, 'ARM Fam| 000007a0 69 6c 79 20 44 61 74 61 20 4d 61 6e 75 61 6c 27 |ily Data Manual'| 000007b0 2c 20 50 72 65 6e 74 69 63 65 2d 48 61 6c 6c 0a |, Prentice-Hall.| 000007c0 31 39 39 30 2e |1990.| 000007c5
.