Home » Archimedes archive » Acorn User » AU 1998-08.adf » Regulars » RTR/Bonus/Serial
RTR/Bonus/Serial
This website contains an archive of files for the Acorn Electron, BBC Micro, Acorn Archimedes, Commodore 16 and Commodore 64 computers, which Dominic Ford has rescued from his private collection of floppy disks and cassettes.
Some of these files were originally commercial releases in the 1980s and 1990s, but they are now widely available online. I assume that copyright over them is no longer being asserted. If you own the copyright and would like files to be removed, please contact me.
| Tape/disk: | Home » Archimedes archive » Acorn User » AU 1998-08.adf » Regulars |
| Filename: | RTR/Bonus/Serial |
| Read OK: | ✔ |
| File size: | 11BF bytes |
| Load address: | 0000 |
| Exec address: | 0000 |
File contents
OS_SerialOp 0
(SWI &57)
Read/write serial status
On entry
R0 = 0 (reason code)
Rl = EOR mask
R2 = AND mask
On exit
R0 preserved
Rl = old value of state
R2 = new value of state
Interrupts
Interrupt status is undefined
Fast interrupts are enabled
Processor Mode
Processor is in SVC mode
Re entrancy
SWI is not re-entrant
Use
The structure of this call is very similar to that of OS_Bytes between SWI &A6 and
SWI &FF. The new state is determined by:
New state = (Old state AND R2) EOR Rl
This call is used to read and write various states of the serial system. These states
are presented as a 32-bit word. The bits in this word represent the following states:
R/W = Read and Write
RO = Read Only
Bit Read Value Meaning
0 R/W 0 No software control. Use RTS handshaking if bit 5 is clear
1 Use XON/XOFF protocol. Bit 5 is ignored. The
hardware will still do CTS handshaking (ie if CTS
goes low then transmission will stop), but RTS
is not forced to go low
1 R/W 0 Use the ~DCD bit. If the ~DCD bit in the status
register goes high, then cause a serial event.
Also, if a character is received when ~DCD is
high, then cause a serial event, and do not enter
the character into the buffer.
1 Ignore the ~DCD bit. Note that some serial chips (GTE and CMD)
have reception and transmission poroblems when this bit is high
2 R/W 0 Use the ~DSR bit. If the ~DSR bit in the status register is high then
do not transmit characters
1 Ignore the state of the ~DSR bit.
3 R/W 0 DTR on (normal operation).
1 DTR off (on 6551 serial chips, cannot use serial port in this state).
4 R/W 0 Use the ~CTS bit. If the ~CTS bit in the status register is high,
then do not transmit characters.
1 Ignore the ~CTS bit (not supported by 6551 serial chips).
5 R/W This bit is ignored if bit O is set. If bit O is clear
0 Use RTS handshaking.
1 Do not use RTS handshaking.
6 R/W 0 Input is not suppressed.
1 Input is suppressed.
7 R/W Users should only modify this bit if RTS handshaking is not in use
0 RTS controlled by handshaking system (low if no RTS handshaking).
1 RTS high.
8 - 15 These bits are reserved for future expansion; do not modify them.
16 RO 0 XOFF not received.
1 XOFF has been received. Transmission is stopped by this occurrence.
17 RO 0 The other end is intended to be in XON state.
1 The other end is intended to be in XOFF state.
When this bit is set, then it means that an XOFF
character has been sent and it will be cleared
when an XON is sent by the buffering software.
Note that the fact that this bit is set does not
imply that the other end has received an XOFF yet.
18 RO 0 The ~DCD bit is low, ie carrier present.
1 The ~DCD bit is high, ie no carrier.
19 RO 0 The ~DSR bit is low, ie 'ready' state.
1 The ~DSR bit is high, ie 'not-ready' state.
20 RO 0 The ring indicator bit is low.
1 The ring indicator bit is high.
21 RO 0 CTS low (clear to send)
1 CTS high (not clear to send)
22 RO 0 User has not manually sent an XOFF.
1 User has manually sent an XOFF.
23 RO 0 Space in receive buffer above threshold.
1 Space in receive buffer below threshold.
24-31 RO These bits are reserved for future expansion; do not modify them.
Note that if XON/XOFF handshaking is used, then OS_Byte 2 1 or 2,2 must be
called beforehand.
RISC OS 2 does not support bits 4-7 and 21-23 inclusive.
Related SWls
OS_Byte 156 (page 2-446)
Related vectors
SerialV
00000000 0a 4f 53 5f 53 65 72 69 61 6c 4f 70 20 30 0a 20 |.OS_SerialOp 0. | 00000010 20 20 20 20 20 28 53 57 49 20 26 35 37 29 0a 0a | (SWI &57)..| 00000020 52 65 61 64 2f 77 72 69 74 65 20 73 65 72 69 61 |Read/write seria| 00000030 6c 20 73 74 61 74 75 73 0a 0a 4f 6e 20 65 6e 74 |l status..On ent| 00000040 72 79 0a 52 30 20 3d 20 30 20 28 72 65 61 73 6f |ry.R0 = 0 (reaso| 00000050 6e 20 63 6f 64 65 29 0a 52 6c 20 3d 20 45 4f 52 |n code).Rl = EOR| 00000060 20 6d 61 73 6b 0a 52 32 20 3d 20 41 4e 44 20 6d | mask.R2 = AND m| 00000070 61 73 6b 0a 0a 0a 4f 6e 20 65 78 69 74 0a 52 30 |ask...On exit.R0| 00000080 20 70 72 65 73 65 72 76 65 64 0a 52 6c 20 3d 20 | preserved.Rl = | 00000090 6f 6c 64 20 76 61 6c 75 65 20 6f 66 20 73 74 61 |old value of sta| 000000a0 74 65 0a 52 32 20 3d 20 6e 65 77 20 76 61 6c 75 |te.R2 = new valu| 000000b0 65 20 6f 66 20 73 74 61 74 65 0a 0a 0a 49 6e 74 |e of state...Int| 000000c0 65 72 72 75 70 74 73 0a 0a 20 20 20 20 20 49 6e |errupts.. In| 000000d0 74 65 72 72 75 70 74 20 73 74 61 74 75 73 20 69 |terrupt status i| 000000e0 73 20 75 6e 64 65 66 69 6e 65 64 0a 20 20 20 20 |s undefined. | 000000f0 20 46 61 73 74 20 69 6e 74 65 72 72 75 70 74 73 | Fast interrupts| 00000100 20 61 72 65 20 65 6e 61 62 6c 65 64 0a 0a 0a 50 | are enabled...P| 00000110 72 6f 63 65 73 73 6f 72 20 4d 6f 64 65 0a 20 20 |rocessor Mode. | 00000120 20 20 20 50 72 6f 63 65 73 73 6f 72 20 69 73 20 | Processor is | 00000130 69 6e 20 53 56 43 20 6d 6f 64 65 0a 0a 52 65 20 |in SVC mode..Re | 00000140 65 6e 74 72 61 6e 63 79 0a 20 20 20 20 20 53 57 |entrancy. SW| 00000150 49 20 69 73 20 6e 6f 74 20 72 65 2d 65 6e 74 72 |I is not re-entr| 00000160 61 6e 74 0a 0a 55 73 65 0a 54 68 65 20 73 74 72 |ant..Use.The str| 00000170 75 63 74 75 72 65 20 6f 66 20 74 68 69 73 20 63 |ucture of this c| 00000180 61 6c 6c 20 69 73 20 76 65 72 79 20 73 69 6d 69 |all is very simi| 00000190 6c 61 72 20 74 6f 20 74 68 61 74 20 6f 66 20 4f |lar to that of O| 000001a0 53 5f 42 79 74 65 73 20 62 65 74 77 65 65 6e 20 |S_Bytes between | 000001b0 53 57 49 20 26 41 36 20 61 6e 64 0a 53 57 49 20 |SWI &A6 and.SWI | 000001c0 26 46 46 2e 20 54 68 65 20 6e 65 77 20 73 74 61 |&FF. The new sta| 000001d0 74 65 20 69 73 20 64 65 74 65 72 6d 69 6e 65 64 |te is determined| 000001e0 20 62 79 3a 0a 0a 20 20 20 20 20 20 20 4e 65 77 | by:.. New| 000001f0 20 73 74 61 74 65 20 3d 20 28 4f 6c 64 20 73 74 | state = (Old st| 00000200 61 74 65 20 41 4e 44 20 52 32 29 20 45 4f 52 20 |ate AND R2) EOR | 00000210 52 6c 0a 0a 54 68 69 73 20 63 61 6c 6c 20 69 73 |Rl..This call is| 00000220 20 75 73 65 64 20 74 6f 20 72 65 61 64 20 61 6e | used to read an| 00000230 64 20 77 72 69 74 65 20 76 61 72 69 6f 75 73 20 |d write various | 00000240 73 74 61 74 65 73 20 6f 66 20 74 68 65 20 73 65 |states of the se| 00000250 72 69 61 6c 20 73 79 73 74 65 6d 2e 20 54 68 65 |rial system. The| 00000260 73 65 20 73 74 61 74 65 73 0a 61 72 65 20 70 72 |se states.are pr| 00000270 65 73 65 6e 74 65 64 20 61 73 20 61 20 33 32 2d |esented as a 32-| 00000280 62 69 74 20 77 6f 72 64 2e 20 54 68 65 20 62 69 |bit word. The bi| 00000290 74 73 20 69 6e 20 74 68 69 73 20 77 6f 72 64 20 |ts in this word | 000002a0 72 65 70 72 65 73 65 6e 74 20 74 68 65 20 66 6f |represent the fo| 000002b0 6c 6c 6f 77 69 6e 67 20 73 74 61 74 65 73 3a 0a |llowing states:.| 000002c0 0a 0a 52 2f 57 20 3d 20 52 65 61 64 20 61 6e 64 |..R/W = Read and| 000002d0 20 57 72 69 74 65 0a 52 4f 20 20 3d 20 52 65 61 | Write.RO = Rea| 000002e0 64 20 4f 6e 6c 79 0a 20 20 20 20 0a 42 69 74 20 |d Only. .Bit | 000002f0 20 52 65 61 64 20 20 20 20 56 61 6c 75 65 20 20 | Read Value | 00000300 20 20 20 20 4d 65 61 6e 69 6e 67 0a 0a 0a 30 20 | Meaning...0 | 00000310 20 20 20 52 2f 57 20 20 20 20 20 20 30 20 20 20 | R/W 0 | 00000320 20 20 20 20 20 20 20 4e 6f 20 73 6f 66 74 77 61 | No softwa| 00000330 72 65 20 63 6f 6e 74 72 6f 6c 2e 20 55 73 65 20 |re control. Use | 00000340 52 54 53 20 68 61 6e 64 73 68 61 6b 69 6e 67 20 |RTS handshaking | 00000350 69 66 20 62 69 74 20 35 20 69 73 20 63 6c 65 61 |if bit 5 is clea| 00000360 72 0a 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 |r.. | 00000370 20 31 20 20 20 20 20 20 20 20 20 20 55 73 65 20 | 1 Use | 00000380 58 4f 4e 2f 58 4f 46 46 20 70 72 6f 74 6f 63 6f |XON/XOFF protoco| 00000390 6c 2e 20 42 69 74 20 35 20 69 73 20 69 67 6e 6f |l. Bit 5 is igno| 000003a0 72 65 64 2e 20 54 68 65 0a 20 20 20 20 20 20 20 |red. The. | 000003b0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | 000003c0 20 20 68 61 72 64 77 61 72 65 20 77 69 6c 6c 20 | hardware will | 000003d0 73 74 69 6c 6c 20 64 6f 20 43 54 53 20 68 61 6e |still do CTS han| 000003e0 64 73 68 61 6b 69 6e 67 20 28 69 65 20 69 66 20 |dshaking (ie if | 000003f0 43 54 53 0a 20 20 20 20 20 20 20 20 20 20 20 20 |CTS. | 00000400 20 20 20 20 20 20 20 20 20 20 20 20 20 67 6f 65 | goe| 00000410 73 20 6c 6f 77 20 74 68 65 6e 20 74 72 61 6e 73 |s low then trans| 00000420 6d 69 73 73 69 6f 6e 20 77 69 6c 6c 20 73 74 6f |mission will sto| 00000430 70 29 2c 20 62 75 74 20 52 54 53 0a 20 20 20 20 |p), but RTS. | 00000440 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | 00000450 20 20 20 20 20 69 73 20 6e 6f 74 20 66 6f 72 63 | is not forc| 00000460 65 64 20 74 6f 20 67 6f 20 6c 6f 77 0a 0a 0a 31 |ed to go low...1| 00000470 20 20 20 20 52 2f 57 20 20 20 20 20 20 20 30 20 | R/W 0 | 00000480 20 20 20 20 20 20 20 20 55 73 65 20 74 68 65 20 | Use the | 00000490 7e 44 43 44 20 62 69 74 2e 20 49 66 20 74 68 65 |~DCD bit. If the| 000004a0 20 7e 44 43 44 20 62 69 74 20 69 6e 20 74 68 65 | ~DCD bit in the| 000004b0 20 73 74 61 74 75 73 0a 20 20 20 20 20 20 20 20 | status. | 000004c0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | 000004d0 20 72 65 67 69 73 74 65 72 20 67 6f 65 73 20 68 | register goes h| 000004e0 69 67 68 2c 20 74 68 65 6e 20 63 61 75 73 65 20 |igh, then cause | 000004f0 61 20 73 65 72 69 61 6c 20 65 76 65 6e 74 2e 0a |a serial event..| 00000500 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | 00000510 20 20 20 20 20 20 20 20 20 41 6c 73 6f 2c 20 69 | Also, i| 00000520 66 20 61 20 63 68 61 72 61 63 74 65 72 20 69 73 |f a character is| 00000530 20 72 65 63 65 69 76 65 64 20 77 68 65 6e 20 7e | received when ~| 00000540 44 43 44 20 69 73 0a 20 20 20 20 20 20 20 20 20 |DCD is. | 00000550 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | 00000560 68 69 67 68 2c 20 74 68 65 6e 20 63 61 75 73 65 |high, then cause| 00000570 20 61 20 73 65 72 69 61 6c 20 65 76 65 6e 74 2c | a serial event,| 00000580 20 61 6e 64 20 64 6f 20 6e 6f 74 20 65 6e 74 65 | and do not ente| 00000590 72 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 |r. | 000005a0 20 20 20 20 20 20 20 20 20 20 20 74 68 65 20 63 | the c| 000005b0 68 61 72 61 63 74 65 72 20 69 6e 74 6f 20 74 68 |haracter into th| 000005c0 65 20 62 75 66 66 65 72 2e 0a 0a 20 20 20 20 20 |e buffer... | 000005d0 20 20 20 20 20 20 20 20 20 31 20 20 20 20 20 20 | 1 | 000005e0 20 20 20 20 49 67 6e 6f 72 65 20 74 68 65 20 7e | Ignore the ~| 000005f0 44 43 44 20 62 69 74 2e 20 4e 6f 74 65 20 74 68 |DCD bit. Note th| 00000600 61 74 20 73 6f 6d 65 20 73 65 72 69 61 6c 20 63 |at some serial c| 00000610 68 69 70 73 20 28 47 54 45 20 61 6e 64 20 43 4d |hips (GTE and CM| 00000620 44 29 20 0a 20 20 20 20 20 20 20 20 20 20 20 20 |D) . | 00000630 20 20 20 20 20 20 20 20 20 20 20 20 20 68 61 76 | hav| 00000640 65 20 72 65 63 65 70 74 69 6f 6e 20 61 6e 64 20 |e reception and | 00000650 74 72 61 6e 73 6d 69 73 73 69 6f 6e 20 70 6f 72 |transmission por| 00000660 6f 62 6c 65 6d 73 20 77 68 65 6e 20 74 68 69 73 |oblems when this| 00000670 20 62 69 74 20 69 73 20 68 69 67 68 0a 0a 32 20 | bit is high..2 | 00000680 20 20 20 52 2f 57 20 20 20 20 20 20 30 20 20 20 | R/W 0 | 00000690 20 20 20 20 20 20 20 55 73 65 20 74 68 65 20 7e | Use the ~| 000006a0 44 53 52 20 62 69 74 2e 20 49 66 20 74 68 65 20 |DSR bit. If the | 000006b0 7e 44 53 52 20 62 69 74 20 69 6e 20 74 68 65 20 |~DSR bit in the | 000006c0 73 74 61 74 75 73 20 72 65 67 69 73 74 65 72 20 |status register | 000006d0 69 73 20 68 69 67 68 20 74 68 65 6e 20 0a 20 20 |is high then . | 000006e0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | 000006f0 20 20 20 20 20 20 20 64 6f 20 6e 6f 74 20 74 72 | do not tr| 00000700 61 6e 73 6d 69 74 20 63 68 61 72 61 63 74 65 72 |ansmit character| 00000710 73 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 |s. | 00000720 31 20 20 20 20 20 20 20 20 20 20 49 67 6e 6f 72 |1 Ignor| 00000730 65 20 74 68 65 20 73 74 61 74 65 20 6f 66 20 74 |e the state of t| 00000740 68 65 20 7e 44 53 52 20 62 69 74 2e 0a 0a 0a 33 |he ~DSR bit....3| 00000750 20 20 20 20 52 2f 57 20 20 20 20 20 20 30 20 20 | R/W 0 | 00000760 20 20 20 20 20 20 20 20 44 54 52 20 6f 6e 20 28 | DTR on (| 00000770 6e 6f 72 6d 61 6c 20 6f 70 65 72 61 74 69 6f 6e |normal operation| 00000780 29 2e 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 |).. | 00000790 20 31 20 20 20 20 20 20 20 20 20 20 44 54 52 20 | 1 DTR | 000007a0 6f 66 66 20 28 6f 6e 20 36 35 35 31 20 73 65 72 |off (on 6551 ser| 000007b0 69 61 6c 20 63 68 69 70 73 2c 20 63 61 6e 6e 6f |ial chips, canno| 000007c0 74 20 75 73 65 20 73 65 72 69 61 6c 20 70 6f 72 |t use serial por| 000007d0 74 20 69 6e 20 74 68 69 73 20 73 74 61 74 65 29 |t in this state)| 000007e0 2e 0a 0a 0a 34 20 20 20 20 52 2f 57 20 20 20 20 |....4 R/W | 000007f0 20 20 30 20 20 20 20 20 20 20 20 20 20 55 73 65 | 0 Use| 00000800 20 74 68 65 20 7e 43 54 53 20 62 69 74 2e 20 49 | the ~CTS bit. I| 00000810 66 20 74 68 65 20 7e 43 54 53 20 62 69 74 20 69 |f the ~CTS bit i| 00000820 6e 20 74 68 65 20 73 74 61 74 75 73 20 72 65 67 |n the status reg| 00000830 69 73 74 65 72 20 69 73 20 68 69 67 68 2c 20 0a |ister is high, .| 00000840 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | 00000850 20 20 20 20 20 20 20 20 20 74 68 65 6e 20 64 6f | then do| 00000860 20 6e 6f 74 20 74 72 61 6e 73 6d 69 74 20 63 68 | not transmit ch| 00000870 61 72 61 63 74 65 72 73 2e 0a 20 20 20 20 20 20 |aracters.. | 00000880 20 20 20 20 20 20 20 20 31 20 20 20 20 20 20 20 | 1 | 00000890 20 20 20 49 67 6e 6f 72 65 20 74 68 65 20 7e 43 | Ignore the ~C| 000008a0 54 53 20 62 69 74 20 28 6e 6f 74 20 73 75 70 70 |TS bit (not supp| 000008b0 6f 72 74 65 64 20 62 79 20 36 35 35 31 20 73 65 |orted by 6551 se| 000008c0 72 69 61 6c 20 63 68 69 70 73 29 2e 0a 0a 0a 35 |rial chips)....5| 000008d0 20 20 20 20 52 2f 57 20 20 20 20 20 20 20 20 20 | R/W | 000008e0 20 20 20 20 20 20 20 20 54 68 69 73 20 62 69 74 | This bit| 000008f0 20 69 73 20 69 67 6e 6f 72 65 64 20 69 66 20 62 | is ignored if b| 00000900 69 74 20 4f 20 69 73 20 73 65 74 2e 20 49 66 20 |it O is set. If | 00000910 62 69 74 20 4f 20 69 73 20 63 6c 65 61 72 0a 20 |bit O is clear. | 00000920 20 20 20 20 20 20 20 20 20 20 20 20 20 30 20 20 | 0 | 00000930 20 20 20 20 20 20 20 20 55 73 65 20 52 54 53 20 | Use RTS | 00000940 68 61 6e 64 73 68 61 6b 69 6e 67 2e 0a 20 20 20 |handshaking.. | 00000950 20 20 20 20 20 20 20 20 20 20 20 31 20 20 20 20 | 1 | 00000960 20 20 20 20 20 20 44 6f 20 6e 6f 74 20 75 73 65 | Do not use| 00000970 20 52 54 53 20 68 61 6e 64 73 68 61 6b 69 6e 67 | RTS handshaking| 00000980 2e 0a 0a 0a 36 20 20 20 20 52 2f 57 20 20 20 20 |....6 R/W | 00000990 20 20 30 20 20 20 20 20 20 20 20 20 20 49 6e 70 | 0 Inp| 000009a0 75 74 20 69 73 20 6e 6f 74 20 73 75 70 70 72 65 |ut is not suppre| 000009b0 73 73 65 64 2e 0a 20 20 20 20 20 20 20 20 20 20 |ssed.. | 000009c0 20 20 20 20 31 20 20 20 20 20 20 20 20 20 20 49 | 1 I| 000009d0 6e 70 75 74 20 69 73 20 73 75 70 70 72 65 73 73 |nput is suppress| 000009e0 65 64 2e 0a 0a 0a 37 20 20 20 20 52 2f 57 20 20 |ed....7 R/W | 000009f0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 55 | U| 00000a00 73 65 72 73 20 73 68 6f 75 6c 64 20 6f 6e 6c 79 |sers should only| 00000a10 20 6d 6f 64 69 66 79 20 74 68 69 73 20 62 69 74 | modify this bit| 00000a20 20 69 66 20 52 54 53 20 68 61 6e 64 73 68 61 6b | if RTS handshak| 00000a30 69 6e 67 20 69 73 20 6e 6f 74 20 69 6e 20 75 73 |ing is not in us| 00000a40 65 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 |e. | 00000a50 30 20 20 20 20 20 20 20 20 20 20 52 54 53 20 63 |0 RTS c| 00000a60 6f 6e 74 72 6f 6c 6c 65 64 20 62 79 20 68 61 6e |ontrolled by han| 00000a70 64 73 68 61 6b 69 6e 67 20 73 79 73 74 65 6d 20 |dshaking system | 00000a80 28 6c 6f 77 20 69 66 20 6e 6f 20 52 54 53 20 68 |(low if no RTS h| 00000a90 61 6e 64 73 68 61 6b 69 6e 67 29 2e 0a 20 20 20 |andshaking).. | 00000aa0 20 20 20 20 20 20 20 20 20 20 20 31 20 20 20 20 | 1 | 00000ab0 20 20 20 20 20 20 52 54 53 20 68 69 67 68 2e 0a | RTS high..| 00000ac0 0a 38 20 2d 20 31 35 20 20 20 20 20 20 20 20 20 |.8 - 15 | 00000ad0 20 20 20 20 20 20 20 20 20 20 54 68 65 73 65 20 | These | 00000ae0 62 69 74 73 20 61 72 65 20 72 65 73 65 72 76 65 |bits are reserve| 00000af0 64 20 66 6f 72 20 66 75 74 75 72 65 20 65 78 70 |d for future exp| 00000b00 61 6e 73 69 6f 6e 3b 20 64 6f 20 6e 6f 74 20 6d |ansion; do not m| 00000b10 6f 64 69 66 79 20 74 68 65 6d 2e 0a 0a 31 36 20 |odify them...16 | 00000b20 20 20 52 4f 20 20 20 20 20 20 20 30 20 20 20 20 | RO 0 | 00000b30 20 20 20 20 20 20 58 4f 46 46 20 6e 6f 74 20 72 | XOFF not r| 00000b40 65 63 65 69 76 65 64 2e 0a 20 20 20 20 20 20 20 |eceived.. | 00000b50 20 20 20 20 20 20 20 31 20 20 20 20 20 20 20 20 | 1 | 00000b60 20 20 58 4f 46 46 20 68 61 73 20 62 65 65 6e 20 | XOFF has been | 00000b70 72 65 63 65 69 76 65 64 2e 20 54 72 61 6e 73 6d |received. Transm| 00000b80 69 73 73 69 6f 6e 20 69 73 20 73 74 6f 70 70 65 |ission is stoppe| 00000b90 64 20 62 79 20 74 68 69 73 20 6f 63 63 75 72 72 |d by this occurr| 00000ba0 65 6e 63 65 2e 0a 0a 31 37 20 20 20 52 4f 20 20 |ence...17 RO | 00000bb0 20 20 20 20 20 30 20 20 20 20 20 20 20 20 20 20 | 0 | 00000bc0 54 68 65 20 6f 74 68 65 72 20 65 6e 64 20 69 73 |The other end is| 00000bd0 20 69 6e 74 65 6e 64 65 64 20 74 6f 20 62 65 20 | intended to be | 00000be0 69 6e 20 58 4f 4e 20 73 74 61 74 65 2e 0a 20 20 |in XON state.. | 00000bf0 20 20 20 20 20 20 20 20 20 20 20 20 31 20 20 20 | 1 | 00000c00 20 20 20 20 20 20 20 54 68 65 20 6f 74 68 65 72 | The other| 00000c10 20 65 6e 64 20 69 73 20 69 6e 74 65 6e 64 65 64 | end is intended| 00000c20 20 74 6f 20 62 65 20 69 6e 20 58 4f 46 46 20 73 | to be in XOFF s| 00000c30 74 61 74 65 2e 0a 20 20 20 20 20 20 20 20 20 20 |tate.. | 00000c40 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 57 | W| 00000c50 68 65 6e 20 74 68 69 73 20 62 69 74 20 69 73 20 |hen this bit is | 00000c60 73 65 74 2c 20 74 68 65 6e 20 69 74 20 6d 65 61 |set, then it mea| 00000c70 6e 73 20 74 68 61 74 20 61 6e 20 58 4f 46 46 0a |ns that an XOFF.| 00000c80 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | 00000c90 20 20 20 20 20 20 20 20 20 63 68 61 72 61 63 74 | charact| 00000ca0 65 72 20 68 61 73 20 62 65 65 6e 20 73 65 6e 74 |er has been sent| 00000cb0 20 61 6e 64 20 69 74 20 77 69 6c 6c 20 62 65 20 | and it will be | 00000cc0 63 6c 65 61 72 65 64 0a 20 20 20 20 20 20 20 20 |cleared. | 00000cd0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | 00000ce0 20 77 68 65 6e 20 61 6e 20 58 4f 4e 20 69 73 20 | when an XON is | 00000cf0 73 65 6e 74 20 62 79 20 74 68 65 20 62 75 66 66 |sent by the buff| 00000d00 65 72 69 6e 67 20 73 6f 66 74 77 61 72 65 2e 0a |ering software..| 00000d10 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | 00000d20 20 20 20 20 20 20 20 20 20 4e 6f 74 65 20 74 68 | Note th| 00000d30 61 74 20 74 68 65 20 66 61 63 74 20 74 68 61 74 |at the fact that| 00000d40 20 74 68 69 73 20 62 69 74 20 69 73 20 73 65 74 | this bit is set| 00000d50 20 64 6f 65 73 20 6e 6f 74 0a 20 20 20 20 20 20 | does not. | 00000d60 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | 00000d70 20 20 20 69 6d 70 6c 79 20 74 68 61 74 20 74 68 | imply that th| 00000d80 65 20 6f 74 68 65 72 20 65 6e 64 20 68 61 73 20 |e other end has | 00000d90 72 65 63 65 69 76 65 64 20 61 6e 20 58 4f 46 46 |received an XOFF| 00000da0 20 79 65 74 2e 0a 0a 31 38 20 20 20 52 4f 20 20 | yet...18 RO | 00000db0 20 20 20 20 20 30 20 20 20 20 20 20 20 20 20 20 | 0 | 00000dc0 54 68 65 20 7e 44 43 44 20 62 69 74 20 69 73 20 |The ~DCD bit is | 00000dd0 6c 6f 77 2c 20 69 65 20 63 61 72 72 69 65 72 20 |low, ie carrier | 00000de0 70 72 65 73 65 6e 74 2e 0a 20 20 20 20 20 20 20 |present.. | 00000df0 20 20 20 20 20 20 20 31 20 20 20 20 20 20 20 20 | 1 | 00000e00 20 20 54 68 65 20 7e 44 43 44 20 62 69 74 20 69 | The ~DCD bit i| 00000e10 73 20 68 69 67 68 2c 20 69 65 20 6e 6f 20 63 61 |s high, ie no ca| 00000e20 72 72 69 65 72 2e 0a 0a 31 39 20 20 20 52 4f 20 |rrier...19 RO | 00000e30 20 20 20 20 20 20 30 20 20 20 20 20 20 20 20 20 | 0 | 00000e40 20 54 68 65 20 7e 44 53 52 20 62 69 74 20 69 73 | The ~DSR bit is| 00000e50 20 6c 6f 77 2c 20 69 65 20 27 72 65 61 64 79 27 | low, ie 'ready'| 00000e60 20 73 74 61 74 65 2e 0a 20 20 20 20 20 20 20 20 | state.. | 00000e70 20 20 20 20 20 20 31 20 20 20 20 20 20 20 20 20 | 1 | 00000e80 20 54 68 65 20 7e 44 53 52 20 62 69 74 20 69 73 | The ~DSR bit is| 00000e90 20 68 69 67 68 2c 20 69 65 20 27 6e 6f 74 2d 72 | high, ie 'not-r| 00000ea0 65 61 64 79 27 20 73 74 61 74 65 2e 0a 0a 32 30 |eady' state...20| 00000eb0 20 20 20 52 4f 20 20 20 20 20 20 20 30 20 20 20 | RO 0 | 00000ec0 20 20 20 20 20 20 20 54 68 65 20 72 69 6e 67 20 | The ring | 00000ed0 69 6e 64 69 63 61 74 6f 72 20 62 69 74 20 69 73 |indicator bit is| 00000ee0 20 6c 6f 77 2e 0a 20 20 20 20 20 20 20 20 20 20 | low.. | 00000ef0 20 20 20 20 31 20 20 20 20 20 20 20 20 20 20 54 | 1 T| 00000f00 68 65 20 72 69 6e 67 20 69 6e 64 69 63 61 74 6f |he ring indicato| 00000f10 72 20 62 69 74 20 69 73 20 68 69 67 68 2e 0a 0a |r bit is high...| 00000f20 32 31 20 20 20 52 4f 20 20 20 20 20 20 20 30 20 |21 RO 0 | 00000f30 20 20 20 20 20 20 20 20 20 43 54 53 20 6c 6f 77 | CTS low| 00000f40 20 28 63 6c 65 61 72 20 74 6f 20 73 65 6e 64 29 | (clear to send)| 00000f50 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 31 |. 1| 00000f60 20 20 20 20 20 20 20 20 20 20 43 54 53 20 68 69 | CTS hi| 00000f70 67 68 20 28 6e 6f 74 20 63 6c 65 61 72 20 74 6f |gh (not clear to| 00000f80 20 73 65 6e 64 29 0a 0a 0a 32 32 20 20 20 52 4f | send)...22 RO| 00000f90 20 20 20 20 20 20 20 30 20 20 20 20 20 20 20 20 | 0 | 00000fa0 20 20 55 73 65 72 20 68 61 73 20 6e 6f 74 20 6d | User has not m| 00000fb0 61 6e 75 61 6c 6c 79 20 73 65 6e 74 20 61 6e 20 |anually sent an | 00000fc0 58 4f 46 46 2e 0a 20 20 20 20 20 20 20 20 20 20 |XOFF.. | 00000fd0 20 20 20 20 31 20 20 20 20 20 20 20 20 20 20 55 | 1 U| 00000fe0 73 65 72 20 68 61 73 20 6d 61 6e 75 61 6c 6c 79 |ser has manually| 00000ff0 20 73 65 6e 74 20 61 6e 20 58 4f 46 46 2e 0a 0a | sent an XOFF...| 00001000 0a 32 33 20 20 20 52 4f 20 20 20 20 20 20 20 30 |.23 RO 0| 00001010 20 20 20 20 20 20 20 20 20 20 53 70 61 63 65 20 | Space | 00001020 69 6e 20 72 65 63 65 69 76 65 20 62 75 66 66 65 |in receive buffe| 00001030 72 20 61 62 6f 76 65 20 74 68 72 65 73 68 6f 6c |r above threshol| 00001040 64 2e 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 |d.. | 00001050 20 31 20 20 20 20 20 20 20 20 20 20 53 70 61 63 | 1 Spac| 00001060 65 20 69 6e 20 72 65 63 65 69 76 65 20 62 75 66 |e in receive buf| 00001070 66 65 72 20 62 65 6c 6f 77 20 74 68 72 65 73 68 |fer below thresh| 00001080 6f 6c 64 2e 0a 0a 0a 32 34 2d 33 31 20 52 4f 20 |old....24-31 RO | 00001090 20 20 20 20 20 54 68 65 73 65 20 62 69 74 73 20 | These bits | 000010a0 61 72 65 20 72 65 73 65 72 76 65 64 20 66 6f 72 |are reserved for| 000010b0 20 66 75 74 75 72 65 20 65 78 70 61 6e 73 69 6f | future expansio| 000010c0 6e 3b 20 64 6f 20 6e 6f 74 20 6d 6f 64 69 66 79 |n; do not modify| 000010d0 20 74 68 65 6d 2e 0a 0a 0a 4e 6f 74 65 20 74 68 | them....Note th| 000010e0 61 74 20 69 66 20 58 4f 4e 2f 58 4f 46 46 20 68 |at if XON/XOFF h| 000010f0 61 6e 64 73 68 61 6b 69 6e 67 20 69 73 20 75 73 |andshaking is us| 00001100 65 64 2c 20 74 68 65 6e 20 4f 53 5f 42 79 74 65 |ed, then OS_Byte| 00001110 20 32 20 31 20 6f 72 20 32 2c 32 20 6d 75 73 74 | 2 1 or 2,2 must| 00001120 20 62 65 0a 63 61 6c 6c 65 64 20 62 65 66 6f 72 | be.called befor| 00001130 65 68 61 6e 64 2e 0a 0a 0a 52 49 53 43 20 4f 53 |ehand....RISC OS| 00001140 20 32 20 64 6f 65 73 20 6e 6f 74 20 73 75 70 70 | 2 does not supp| 00001150 6f 72 74 20 62 69 74 73 20 34 2d 37 20 61 6e 64 |ort bits 4-7 and| 00001160 20 32 31 2d 32 33 20 69 6e 63 6c 75 73 69 76 65 | 21-23 inclusive| 00001170 2e 0a 0a 52 65 6c 61 74 65 64 20 53 57 6c 73 0a |...Related SWls.| 00001180 0a 20 20 20 20 20 4f 53 5f 42 79 74 65 20 31 35 |. OS_Byte 15| 00001190 36 20 28 70 61 67 65 20 32 2d 34 34 36 29 0a 0a |6 (page 2-446)..| 000011a0 52 65 6c 61 74 65 64 20 76 65 63 74 6f 72 73 0a |Related vectors.| 000011b0 0a 20 20 20 20 20 53 65 72 69 61 6c 56 0a 0a |. SerialV..| 000011bf
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