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12-03-89/T\TTX01
This website contains an archive of files for the Acorn Electron, BBC Micro, Acorn Archimedes, Commodore 16 and Commodore 64 computers, which Dominic Ford has rescued from his private collection of floppy disks and cassettes.
Some of these files were originally commercial releases in the 1980s and 1990s, but they are now widely available online. I assume that copyright over them is no longer being asserted. If you own the copyright and would like files to be removed, please contact me.
| Tape/disk: | Home » CEEFAX disks » telesoftware14.adl |
| Filename: | 12-03-89/T\TTX01 |
| Read OK: | ✔ |
| File size: | 44DD bytes |
| Load address: | 0000 |
| Exec address: | FFFFFFFF |
File contents
Interfacing with the Acorn Teletext Adaptor - by - Gordon Horsington
--------------------------------------------------------------------
Module 1. Teletext generated interrupts
---------------------------------------
In the next six Teletext modules I will explain how to write software to
interface with the Acorn Teletext adaptor hardware without using either
the ATS or the TFS. In order to understand these modules you will need to
be familiar with the use of maskable interrupts on the BBC microcomputer.
The Acorn Teletext adaptor uses maskable interrupts to inform the BBC
computer that it has data ready for processing. Maskable interrupts can be
intercepted on the BBC computer and re-directed to an address specified by
the user. There are two interrupt request vectors which could be used to
make this interception. Interrupt Request Vector 1 (IRQ1V) at &204 and
&205 is used for high priority interrupts and you should avoid using this
vector. The low priority Interrupt Request Vector 2 (IRQ2V) at &206 and
&207 should be used to intercept the Teletext generated interrupts.
The BBC computer is connected to the Acorn Teletext adaptor using the 1
MHz bus. The Teletext hardware is mapped onto 4 bytes of page &FC in the
I/O processor memory. This page is usually known as FRED and it is
reserved for the 1 MHz bus. The four bytes reserved for the Teletext
adaptor, from &FC10 to &FC13, are used for all communication between the
BBC computer and the Teletext hardware. Using these four bytes is the only
direct way of reading from or writing to the adaptor and they are used by
all Acorn Teletext adaptor software including the ATS and the TFS.
Osbyte calls &92 and &93 can be used to communicate with page &FC. Osbyte
&92 is used to write to FRED and Osbyte &93 to read from FRED. Although
operating system calls have been provided for reading from and writing to
FRED, you should avoid using them in interrupt processing software
whenever possible. The reason for avoiding the operating system calls is
that if a foreground task is using an operating system routine which is
also used by an interrupt routine, and the operating system routine is not
re-entrant, your program will crash.
All Osbyte calls have a time penalty associated with their use and, for
reasons which will explained later in this module, it is necessary to use
programs which have been optimized for speed when processing the
interrupts generated by the Teletext adaptor. It is much quicker to peek
and poke the registers directly as well as much safer. This faster method
of using the Teletext registers directly does not cause any Tube
compatibility problems because interrupts generated by I/O processor
hardware, such as the Teletext adaptor, are not passed to a second
processor. Teletext generated interrupts must be dealt with by software
running in the I/O processor.
The Acorn Teletext adaptor contains 1k of memory arranged as 16 rows of 64
bytes. This memory can be accessed and controlled using the Teletext
registers. The five Teletext adaptor registers are mapped onto the four
bytes from &FC10 to &FC13. These registers are known as the status
register (&FC10), the control register (also at &FC10), the row register
(&FC11), the data register (&FC12) and the status clear register (&FC13).
Status Register (&FC10)
-----------------------
The eight bit status register at &FC10 is the read-only status register of
the Teletext adaptor. The bits of the status register have the following
interpretation:
D0-3 Link selectable options.
D4 Frame Sync. Set by the TV frame sync pulse and reset by writing to
&FC13.
D5 Data Entry Window. High during TTX portion of TV signal. If D7 is low
and TTX unit enabled the TTX unit locks out the CPU during this time.
D6 Data Overrun. Set High if status is not cleared before next data
entry window.
D7 Interrupt. Set High by the trailing edge of the data entry window.
Control Register (&FC10)
------------------------
The eight bit control register at &FC10 is the write-only control register
of the Teletext adaptor. The bits of the control register have the
following functions:
D0-1 Channel number (0-3)
D2 TTX Enable. Set High to enable TTX reception. Set Low to allow use of
1K by computer. (16*64 bytes)
D3 Interrupt Enable. Set High to enable interrupts. Set Low to disable
interrupts. No effect on working of TTX unit.
D4 AFC Control. Set Low to disable AFC and allow tuning. Set High to
enable automatic frequency control.
D5 Spare.
D6-7 Not used, not latched.
Row Register (&FC11)
--------------------
The four bit row register at &FC11 is the write-only row register of the
Teletext adaptor. The bits of the row register have the following
functions:
D0-3 This 4 bit register controls which of the 16 64 byte long rows of the
adaptor's memory will be accessed by the data register. Setting this
register resets the column count (internal) to zero.
Data Register (&FC12)
---------------------
The eight bit Data Register at &FC12 is the read and write data register
of the Teletext adaptor. The bits of the data register have the following
interpretation:
D0-7 This 8 bit register is used to read from and write to the 16*64 bytes
in the TTX adaptor. When the Row register is written to, an internal
column count is set to zero. Every time the data register is read or
written to, the column count is incremented. Thus successive reads
from the data register return successive bytes from the selected row.
Status Clear Register (&FC13)
-----------------------------
The eight bit status clear register at &FC13 is the read-and-write clear
status register of the Teletext adaptor. The bits of the clear status
register have the following interpretation:
D0-7 Reading or writing to this register clears the status flags. This
must be done at the end of any data collection routine, otherwise the
Data Overrun flag will be set (bit 6 of the status register).
When you design programs which bypass the ATS ROM and interface directly
with the Teletext hardware it is a good idea to consider using either a
BASIC or a machine code foreground task to update the screen and an
interrupt driven machine code background task to process the Teletext
interrupts. This type of design will be used in all the programs used to
illustrate the Teletext modules 1 to 7.
The example program associated with this module shows you how to re-direct
the IRQ2V vector to point to an interrupt handling routine and how that
routine can recognise and process Teletext generated interrupts. The
program COUNTER is perhaps the most simple type of interrupt processing
possible with the Teletext adaptor. The program recognises Teletext
interrupts and counts how many interrupts are generated while the program
is active. When the escape key is pressed the program calculates the rate
at which the interrupts have been generated.
The program COUNTER uses BASIC to assemble and call a machine code
program. The machine code can be divided into a foreground task (lines 500
to 660), which prints the contents of a four byte decimal counter, and a
background task (lines 780 to 1170), which processes the Teletext
generated interrupts. This program illustrates how the control register is
used to enable the Teletext adaptor and select a TV channel, and also how
the clear status register must be used after processing every Teletext
interrupt.
Bits 0 to 4 of the control register are used to enable the Teletext
adaptor and select the required channel. Bits 0 and 1 are used to select
the channel, bit 2 is set high to enable Teletext reception, bit 3 is set
high to enable Teletext generated interrupts and bit 4 is set high to
enable the automatic frequency control. When you use the control register
to enable the Teletext adaptor you will only normally write one of four
values to the register. These numbers are in the range from &1C to &1F.
&1C %00011100 Enable AFC, enable interrupts, enable TTX, channel 0
&1D %00011101 Enable AFC, enable interrupts, enable TTX, channel 1
&1E %00011110 Enable AFC, enable interrupts, enable TTX, channel 2
&1F %00011111 Enable AFC, enable interrupts, enable TTX, channel 3
One of these four values is selected in lines 80 to 120 and written to
the control register in lines 480 and 490 of COUNTER. The Teletext adaptor
is disabled by writing the value &00 to the control register (lines 690
and 700). All the demonstration programs in the Acorn Teletext modules
will prompt for a channel number in the range from 1 to 4 even though the
adaptor uses channel numbers 0 to 3. It seems to be sensible to use the
range 1 to 4 which corresponds with BBC1, BBC2 and Channel 4 better than
the range 0 to 3. For this reason the number &1B (not &1C) is added to the
channel number in line 100 to give the required range of values for the
control register.
An interrupt generated by the Teletext adaptor can be recognised by
polling the status register. Bit 7 of the status register is set when the
Teletext adaptor generates an interrupt. The program COUNTER intercepts
all unrecognised maskable interrupts offered to the IRQ2 vector and polls
the status register (line 790) to see if the Teletext adaptor was the
source of the unrecognised interrupt. If the adaptor was not the source of
the interrupt it is passed on to the original interrupt handling routine
(line 810). If the adaptor was the source of the interrupt it is processed
by the program and a return is made using an RTI instruction (line 1170).
Before returning from a Teletext generated interrupt it is essential to
clear all 16 rows in the Teletext adaptor by selecting each row and
writing the number zero to the adaptor (lines 1030 to 1090). A row is
selected by writing the row number into the row register and the row is
cleared by storing zero in the first available byte in the row. This byte
is called the framing code and will be explained in detail in module 2.
After clearing the adaptor memory, it is also necessary to either read
from or write to the status clear register to clear the status flags (line
1100). All Teletext processing routines must do this before returning from
an interrupt. Failure to do so will produce a data overrun error.
Before chaining the program COUNTER you can disable the ATS ROM by typing
the command *NOTTX. This should convince sceptics that the program is
completely independant of the ATS. It is not necessary to disable the ATS
in this way to use any of the demonstration programs with the Acorn
adaptor because the ATS should not interfere with them in any way but, if
you have a sideways RAM / shadow RAM board installed in a BBC B computer,
you may have to use *NOTTX and alter irq2v to irq1v to get the program to
work. If you have to modify this program you will have to modify all the
programs associated with Teletext modules 1 to 7.
Chain the program COUNTER, let it run for a little while and then press
the Escape key. When I used the program I found that the Teletext adaptor
produced 50.05 interrupts a second. This corresponds very well with the 50
Hz field flyback interval and the difference may be due to a slight
inaccuracy in the BBC computer's timer.
A Teletext generated interrupt indicates that data are available for
processing and it is up to you to ensure that all processing of the
Teletext interrupt is complete well before 20 milliseconds have elapsed
when another Teletext interrupt can be expected. If a program does not
clear the status flags and execute an RTI before the 20 millisecond
deadline then the least problem you can expect is a data overrun error. It
is much more likely that any interrupt handling routine which takes
anything like 20 milliseconds will hang up the computer completely and
very quickly.
You must always design your background tasks to deal with the interrupts
as quickly as possible. This is certainly not a problem with a simple
program like COUNTER but it something to keep in mind in the later modules
when the design of frame grabbers and keyword searching will be
considered.
If a foreground task needs more than 20 milliseconds to analyse a data
packet then you could consider either disabling the Teletext hardware or
"dumping" unwanted data after reading the data you want to process into
the computer memory. Although this is a possible method of controlling the
hardware you must use it with care. Any processing that takes more than 20
milliseconds will probably be written in BASIC or very inefficient machine
code and you must remember that disabling the hardware or dumping data can
result in losing the very data you want to process. You can only expect to
get away with very long data processing times when your program is looking
for single data packets, such as the Television Service Data Packet, which
arrive at infrequent intervals.
10 REM> COUNTER
20 MODE7
30 DIM mcode &200 :REM: space for machine code
40 PROCmcode :REM: assemble machine code
50 ttx$=CHR$(141)+CHR$(132)+CHR$(157)+CHR$(131)
+"TTX interrupt counter "+CHR$(156)
60 PRINTTAB(5,3)ttx$
70 PRINTTAB(5,4)ttx$
80 INPUTTAB(9,8)"TV channel (1-4) = "answer$
90 VDU23,1,0;0;0;0;
100 ?channel=EVAL("&"+LEFT$(answer$,1))+&1B
110 IF ?channel < &1C THEN ?channel = &1C
120 IF ?channel > &1F THEN ?channel = &1F
130 TIME=0
140 CALL mcode
150 time=TIME/100
160 count=EVAL(STR$~(!counter))
170 at%=@%
180 @%=&20205
190 PRINTTAB(6,16);count/time;" interrupts per second"
200 @%=at%
210 VDU31,0,22,23,1,1;0;0;0;
220 END
230 DEFPROCmcode
240 channel=&70 :REM: TV channel
250 savereg=&FC :REM: interrupt accumulator save register
260 escape=&FF :REM: escape flag
270 irq2v=&206 :REM: IRQ2 vector
280 ttxcontrol=&FC10 :REM: TTX control register, write only
290 ttxstatus=&FC10 :REM: TTX status register, read only
300 rowreg=&FC11 :REM: TTX row register, write only
310 datareg=&FC12 :REM: TTX data register, read & write
320 statclr=&FC13 :REM: TTX clear status register, read & write
330 oswrch=&FFEE
340 osbyte=&FFF4
350 FOR pass=0 TO 2 STEP 2
360 P%=mcode
370 [ OPT pass
380 LDX irq2v \ load secondary interrupt vector
390 LDY irq2v+1
400 STX oldirq2v \ save secondary interrupt vector
410 STY oldirq2v+1
420 LDX #interrupt MOD 256 \ install new interrupt routine
430 LDY #interrupt DIV 256
440 SEI \ disable interrupts when altering vector
450 STX irq2v
460 STY irq2v+1
470 CLI \ re-enable interrupts
480 LDA channel \ load (channel number + #&1C)
490 STA ttxcontrol \ enable TTX
500 .mainloop
510 LDA #&1F \ decimal 31
520 JSR oswrch
530 LDA #&0F \ decimal 15
540 JSR oswrch
550 LDA #&0C \ decimal 12
560 JSR oswrch \ VDU 31,14,14
570 LDA counter+3
580 JSR printbcd \ print 4 byte counter in hex.
590 LDA counter+2
600 JSR printbcd
610 LDA counter+1
620 JSR printbcd
630 LDA counter
640 JSR printbcd
650 LDA escape \ poll escape flag
660 BPL mainloop \ branch if escape not pressed
670 LDA #&7E
680 JSR osbyte \ acknowledge escape
690 LDA #&00
700 STA ttxcontrol \ disable TTX
710 LDX oldirq2v \ load original vector
720 LDY oldirq2v+1
730 SEI \ disable interrupts when altering vector
740 STX irq2v \ restore original vector
750 STY irq2v+1
760 CLI \ re-enable interrupts
770 RTS \ return to BASIC
780 .interrupt
790 BIT ttxstatus \ poll TTX hardware
800 BMI ttxinter \ branch if TTX interrupt
810 JMP (oldirq2v) \ not TTX interrupt
820 .ttxinter
830 LDA savereg \ interrupt accumulator save register
840 PHA \ push interrupt accumulator save register
850 TXA
860 PHA \ push X
870 TYA
880 PHA \ push Y
890 SED
900 CLC
910 LDA #&01
920 ADC counter \ add 1 for every TTX interrupt
930 STA counter
940 LDA #&00
950 ADC counter+1
960 STA counter+1
970 LDA #&00
980 ADC counter+2
990 STA counter+2
1000 LDA #&00
1010 ADC counter+3
1020 STA counter+3
1030 LDA #&00
1040 LDY #&0F \ clear 16 rows in adaptor
1050 .clearloop
1060 STY rowreg
1070 STA datareg
1080 DEY
1090 BPL clearloop
1100 STA statclr \ clear status flags before returning
1110 PLA
1120 TAY \ restore Y
1130 PLA
1140 TAX \ restore X
1150 PLA
1160 STA savereg \ restore interrupt accumulator save register
1170 RTI \ return from interrupt
1180 .printbcd
1190 PHA
1200 LSR A
1210 LSR A
1220 LSR A
1230 LSR A
1240 JSR nybble
1250 PLA
1260 .nybble
1270 AND #&0F \ decimal 15
1280 SED
1290 CLC
1300 ADC #&90 \ decimal 144
1310 ADC #&40 \ decimal 64
1320 CLD
1330 JMP oswrch
1340 .counter
1350 EQUD &00
1360 .oldirq2v
1370 EQUW &00
1380 ]
1390 NEXT
1400 ENDPROC
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00000020 65 78 74 20 41 64 61 70 74 6f 72 20 2d 20 62 79 |ext Adaptor - by|
00000030 20 2d 20 47 6f 72 64 6f 6e 20 48 6f 72 73 69 6e | - Gordon Horsin|
00000040 67 74 6f 6e 0d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |gton.-----------|
00000050 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |----------------|
*
00000080 2d 2d 2d 2d 2d 2d 2d 2d 2d 0d 0d 4d 6f 64 75 6c |---------..Modul|
00000090 65 20 31 2e 20 54 65 6c 65 74 65 78 74 20 67 65 |e 1. Teletext ge|
000000a0 6e 65 72 61 74 65 64 20 69 6e 74 65 72 72 75 70 |nerated interrup|
000000b0 74 73 0d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |ts.-------------|
000000c0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |----------------|
000000d0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 0d 0d 49 6e 20 74 |----------..In t|
000000e0 68 65 20 6e 65 78 74 20 73 69 78 20 54 65 6c 65 |he next six Tele|
000000f0 74 65 78 74 20 6d 6f 64 75 6c 65 73 20 49 20 77 |text modules I w|
00000100 69 6c 6c 20 65 78 70 6c 61 69 6e 20 68 6f 77 20 |ill explain how |
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00000130 69 74 68 20 74 68 65 20 41 63 6f 72 6e 20 54 65 |ith the Acorn Te|
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00000150 61 72 64 77 61 72 65 20 77 69 74 68 6f 75 74 20 |ardware without |
00000160 75 73 69 6e 67 20 65 69 74 68 65 72 0d 74 68 65 |using either.the|
00000170 20 41 54 53 20 6f 72 20 74 68 65 20 54 46 53 2e | ATS or the TFS.|
00000180 20 49 6e 20 6f 72 64 65 72 20 74 6f 20 75 6e 64 | In order to und|
00000190 65 72 73 74 61 6e 64 20 74 68 65 73 65 20 6d 6f |erstand these mo|
000001a0 64 75 6c 65 73 20 79 6f 75 20 77 69 6c 6c 20 6e |dules you will n|
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000001c0 61 72 20 77 69 74 68 20 74 68 65 20 75 73 65 20 |ar with the use |
000001d0 6f 66 20 6d 61 73 6b 61 62 6c 65 20 69 6e 74 65 |of maskable inte|
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000001f0 43 20 6d 69 63 72 6f 63 6f 6d 70 75 74 65 72 2e |C microcomputer.|
00000200 0d 0d 54 68 65 20 41 63 6f 72 6e 20 54 65 6c 65 |..The Acorn Tele|
00000210 74 65 78 74 20 61 64 61 70 74 6f 72 20 75 73 65 |text adaptor use|
00000220 73 20 6d 61 73 6b 61 62 6c 65 20 69 6e 74 65 72 |s maskable inter|
00000230 72 75 70 74 73 20 74 6f 20 69 6e 66 6f 72 6d 20 |rupts to inform |
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00000260 61 20 72 65 61 64 79 20 66 6f 72 20 70 72 6f 63 |a ready for proc|
00000270 65 73 73 69 6e 67 2e 20 4d 61 73 6b 61 62 6c 65 |essing. Maskable|
00000280 20 69 6e 74 65 72 72 75 70 74 73 20 63 61 6e 20 | interrupts can |
00000290 62 65 0d 69 6e 74 65 72 63 65 70 74 65 64 20 6f |be.intercepted o|
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00000410 73 65 64 20 74 6f 20 69 6e 74 65 72 63 65 70 74 |sed to intercept|
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00000470 54 65 6c 65 74 65 78 74 20 61 64 61 70 74 6f 72 |Teletext adaptor|
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00000510 6e 64 20 69 74 20 69 73 0d 72 65 73 65 72 76 65 |nd it is.reserve|
00000520 64 20 66 6f 72 20 74 68 65 20 31 20 4d 48 7a 20 |d for the 1 MHz |
00000530 62 75 73 2e 20 54 68 65 20 66 6f 75 72 20 62 79 |bus. The four by|
00000540 74 65 73 20 72 65 73 65 72 76 65 64 20 66 6f 72 |tes reserved for|
00000550 20 74 68 65 20 54 65 6c 65 74 65 78 74 0d 61 64 | the Teletext.ad|
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000005b0 74 65 72 20 61 6e 64 20 74 68 65 20 54 65 6c 65 |ter and the Tele|
000005c0 74 65 78 74 20 68 61 72 64 77 61 72 65 2e 20 55 |text hardware. U|
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00000610 77 72 69 74 69 6e 67 20 74 6f 20 74 68 65 20 61 |writing to the a|
00000620 64 61 70 74 6f 72 20 61 6e 64 20 74 68 65 79 20 |daptor and they |
00000630 61 72 65 20 75 73 65 64 20 62 79 0d 61 6c 6c 20 |are used by.all |
00000640 41 63 6f 72 6e 20 54 65 6c 65 74 65 78 74 20 61 |Acorn Teletext a|
00000650 64 61 70 74 6f 72 20 73 6f 66 74 77 61 72 65 20 |daptor software |
00000660 69 6e 63 6c 75 64 69 6e 67 20 74 68 65 20 41 54 |including the AT|
00000670 53 20 61 6e 64 20 74 68 65 20 54 46 53 2e 0d 0d |S and the TFS...|
00000680 4f 73 62 79 74 65 20 63 61 6c 6c 73 20 26 39 32 |Osbyte calls &92|
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00003820 53 54 59 20 6f 6c 64 69 72 71 32 76 2b 31 0d 20 |STY oldirq2v+1. |
00003830 20 34 32 30 20 20 20 20 20 20 20 20 20 4c 44 58 | 420 LDX|
00003840 20 23 69 6e 74 65 72 72 75 70 74 20 4d 4f 44 20 | #interrupt MOD |
00003850 32 35 36 20 5c 20 69 6e 73 74 61 6c 6c 20 6e 65 |256 \ install ne|
00003860 77 20 69 6e 74 65 72 72 75 70 74 20 72 6f 75 74 |w interrupt rout|
00003870 69 6e 65 0d 20 20 34 33 30 20 20 20 20 20 20 20 |ine. 430 |
00003880 20 20 4c 44 59 20 23 69 6e 74 65 72 72 75 70 74 | LDY #interrupt|
00003890 20 44 49 56 20 32 35 36 0d 20 20 34 34 30 20 20 | DIV 256. 440 |
000038a0 20 20 20 20 20 20 20 53 45 49 20 20 20 20 20 20 | SEI |
000038b0 20 20 20 20 20 5c 20 64 69 73 61 62 6c 65 20 69 | \ disable i|
000038c0 6e 74 65 72 72 75 70 74 73 20 77 68 65 6e 20 61 |nterrupts when a|
000038d0 6c 74 65 72 69 6e 67 20 76 65 63 74 6f 72 0d 20 |ltering vector. |
000038e0 20 34 35 30 20 20 20 20 20 20 20 20 20 53 54 58 | 450 STX|
000038f0 20 69 72 71 32 76 0d 20 20 34 36 30 20 20 20 20 | irq2v. 460 |
00003900 20 20 20 20 20 53 54 59 20 69 72 71 32 76 2b 31 | STY irq2v+1|
00003910 0d 20 20 34 37 30 20 20 20 20 20 20 20 20 20 43 |. 470 C|
00003920 4c 49 20 20 20 20 20 20 20 20 20 20 20 5c 20 72 |LI \ r|
00003930 65 2d 65 6e 61 62 6c 65 20 69 6e 74 65 72 72 75 |e-enable interru|
00003940 70 74 73 0d 20 20 34 38 30 20 20 20 20 20 20 20 |pts. 480 |
00003950 20 20 4c 44 41 20 63 68 61 6e 6e 65 6c 20 20 20 | LDA channel |
00003960 5c 20 6c 6f 61 64 20 28 63 68 61 6e 6e 65 6c 20 |\ load (channel |
00003970 6e 75 6d 62 65 72 20 2b 20 23 26 31 43 29 0d 20 |number + #&1C). |
00003980 20 34 39 30 20 20 20 20 20 20 20 20 20 53 54 41 | 490 STA|
00003990 20 74 74 78 63 6f 6e 74 72 6f 6c 20 5c 20 65 6e | ttxcontrol \ en|
000039a0 61 62 6c 65 20 54 54 58 0d 20 20 35 30 30 20 2e |able TTX. 500 .|
000039b0 6d 61 69 6e 6c 6f 6f 70 0d 20 20 35 31 30 20 20 |mainloop. 510 |
000039c0 20 20 20 20 20 20 20 4c 44 41 20 23 26 31 46 20 | LDA #&1F |
000039d0 20 20 20 20 20 5c 20 64 65 63 69 6d 61 6c 20 33 | \ decimal 3|
000039e0 31 0d 20 20 35 32 30 20 20 20 20 20 20 20 20 20 |1. 520 |
000039f0 4a 53 52 20 6f 73 77 72 63 68 0d 20 20 35 33 30 |JSR oswrch. 530|
00003a00 20 20 20 20 20 20 20 20 20 4c 44 41 20 23 26 30 | LDA #&0|
00003a10 46 20 20 20 20 20 20 5c 20 64 65 63 69 6d 61 6c |F \ decimal|
00003a20 20 31 35 0d 20 20 35 34 30 20 20 20 20 20 20 20 | 15. 540 |
00003a30 20 20 4a 53 52 20 6f 73 77 72 63 68 0d 20 20 35 | JSR oswrch. 5|
00003a40 35 30 20 20 20 20 20 20 20 20 20 4c 44 41 20 23 |50 LDA #|
00003a50 26 30 43 20 20 20 20 20 20 5c 20 64 65 63 69 6d |&0C \ decim|
00003a60 61 6c 20 31 32 0d 20 20 35 36 30 20 20 20 20 20 |al 12. 560 |
00003a70 20 20 20 20 4a 53 52 20 6f 73 77 72 63 68 20 20 | JSR oswrch |
00003a80 20 20 5c 20 56 44 55 20 33 31 2c 31 34 2c 31 34 | \ VDU 31,14,14|
00003a90 0d 20 20 35 37 30 20 20 20 20 20 20 20 20 20 4c |. 570 L|
00003aa0 44 41 20 63 6f 75 6e 74 65 72 2b 33 0d 20 20 35 |DA counter+3. 5|
00003ab0 38 30 20 20 20 20 20 20 20 20 20 4a 53 52 20 70 |80 JSR p|
00003ac0 72 69 6e 74 62 63 64 20 20 5c 20 70 72 69 6e 74 |rintbcd \ print|
00003ad0 20 34 20 62 79 74 65 20 63 6f 75 6e 74 65 72 20 | 4 byte counter |
00003ae0 69 6e 20 68 65 78 2e 0d 20 20 35 39 30 20 20 20 |in hex.. 590 |
00003af0 20 20 20 20 20 20 4c 44 41 20 63 6f 75 6e 74 65 | LDA counte|
00003b00 72 2b 32 0d 20 20 36 30 30 20 20 20 20 20 20 20 |r+2. 600 |
00003b10 20 20 4a 53 52 20 70 72 69 6e 74 62 63 64 0d 20 | JSR printbcd. |
00003b20 20 36 31 30 20 20 20 20 20 20 20 20 20 4c 44 41 | 610 LDA|
00003b30 20 63 6f 75 6e 74 65 72 2b 31 0d 20 20 36 32 30 | counter+1. 620|
00003b40 20 20 20 20 20 20 20 20 20 4a 53 52 20 70 72 69 | JSR pri|
00003b50 6e 74 62 63 64 0d 20 20 36 33 30 20 20 20 20 20 |ntbcd. 630 |
00003b60 20 20 20 20 4c 44 41 20 63 6f 75 6e 74 65 72 0d | LDA counter.|
00003b70 20 20 36 34 30 20 20 20 20 20 20 20 20 20 4a 53 | 640 JS|
00003b80 52 20 70 72 69 6e 74 62 63 64 0d 20 20 36 35 30 |R printbcd. 650|
00003b90 20 20 20 20 20 20 20 20 20 4c 44 41 20 65 73 63 | LDA esc|
00003ba0 61 70 65 20 20 20 20 5c 20 70 6f 6c 6c 20 65 73 |ape \ poll es|
00003bb0 63 61 70 65 20 66 6c 61 67 0d 20 20 36 36 30 20 |cape flag. 660 |
00003bc0 20 20 20 20 20 20 20 20 42 50 4c 20 6d 61 69 6e | BPL main|
00003bd0 6c 6f 6f 70 20 20 5c 20 62 72 61 6e 63 68 20 69 |loop \ branch i|
00003be0 66 20 65 73 63 61 70 65 20 6e 6f 74 20 70 72 65 |f escape not pre|
00003bf0 73 73 65 64 0d 20 20 36 37 30 20 20 20 20 20 20 |ssed. 670 |
00003c00 20 20 20 4c 44 41 20 23 26 37 45 0d 20 20 36 38 | LDA #&7E. 68|
00003c10 30 20 20 20 20 20 20 20 20 20 4a 53 52 20 6f 73 |0 JSR os|
00003c20 62 79 74 65 20 20 20 20 5c 20 61 63 6b 6e 6f 77 |byte \ acknow|
00003c30 6c 65 64 67 65 20 65 73 63 61 70 65 0d 20 20 36 |ledge escape. 6|
00003c40 39 30 20 20 20 20 20 20 20 20 20 4c 44 41 20 23 |90 LDA #|
00003c50 26 30 30 0d 20 20 37 30 30 20 20 20 20 20 20 20 |&00. 700 |
00003c60 20 20 53 54 41 20 74 74 78 63 6f 6e 74 72 6f 6c | STA ttxcontrol|
00003c70 20 5c 20 64 69 73 61 62 6c 65 20 54 54 58 0d 20 | \ disable TTX. |
00003c80 20 37 31 30 20 20 20 20 20 20 20 20 20 4c 44 58 | 710 LDX|
00003c90 20 6f 6c 64 69 72 71 32 76 20 20 5c 20 6c 6f 61 | oldirq2v \ loa|
00003ca0 64 20 6f 72 69 67 69 6e 61 6c 20 76 65 63 74 6f |d original vecto|
00003cb0 72 0d 20 20 37 32 30 20 20 20 20 20 20 20 20 20 |r. 720 |
00003cc0 4c 44 59 20 6f 6c 64 69 72 71 32 76 2b 31 0d 20 |LDY oldirq2v+1. |
00003cd0 20 37 33 30 20 20 20 20 20 20 20 20 20 53 45 49 | 730 SEI|
00003ce0 20 20 20 20 20 20 20 20 20 20 20 5c 20 64 69 73 | \ dis|
00003cf0 61 62 6c 65 20 69 6e 74 65 72 72 75 70 74 73 20 |able interrupts |
00003d00 77 68 65 6e 20 61 6c 74 65 72 69 6e 67 20 76 65 |when altering ve|
00003d10 63 74 6f 72 0d 20 20 37 34 30 20 20 20 20 20 20 |ctor. 740 |
00003d20 20 20 20 53 54 58 20 69 72 71 32 76 20 20 20 20 | STX irq2v |
00003d30 20 5c 20 72 65 73 74 6f 72 65 20 6f 72 69 67 69 | \ restore origi|
00003d40 6e 61 6c 20 76 65 63 74 6f 72 0d 20 20 37 35 30 |nal vector. 750|
00003d50 20 20 20 20 20 20 20 20 20 53 54 59 20 69 72 71 | STY irq|
00003d60 32 76 2b 31 0d 20 20 37 36 30 20 20 20 20 20 20 |2v+1. 760 |
00003d70 20 20 20 43 4c 49 20 20 20 20 20 20 20 20 20 20 | CLI |
00003d80 20 5c 20 72 65 2d 65 6e 61 62 6c 65 20 69 6e 74 | \ re-enable int|
00003d90 65 72 72 75 70 74 73 0d 20 20 37 37 30 20 20 20 |errupts. 770 |
00003da0 20 20 20 20 20 20 52 54 53 20 20 20 20 20 20 20 | RTS |
00003db0 20 20 20 20 5c 20 72 65 74 75 72 6e 20 74 6f 20 | \ return to |
00003dc0 42 41 53 49 43 0d 20 20 37 38 30 20 2e 69 6e 74 |BASIC. 780 .int|
00003dd0 65 72 72 75 70 74 0d 20 20 37 39 30 20 20 20 20 |errupt. 790 |
00003de0 20 20 20 20 20 42 49 54 20 74 74 78 73 74 61 74 | BIT ttxstat|
00003df0 75 73 20 5c 20 70 6f 6c 6c 20 54 54 58 20 68 61 |us \ poll TTX ha|
00003e00 72 64 77 61 72 65 0d 20 20 38 30 30 20 20 20 20 |rdware. 800 |
00003e10 20 20 20 20 20 42 4d 49 20 74 74 78 69 6e 74 65 | BMI ttxinte|
00003e20 72 20 20 5c 20 62 72 61 6e 63 68 20 69 66 20 54 |r \ branch if T|
00003e30 54 58 20 69 6e 74 65 72 72 75 70 74 0d 20 20 38 |TX interrupt. 8|
00003e40 31 30 20 20 20 20 20 20 20 20 20 4a 4d 50 20 28 |10 JMP (|
00003e50 6f 6c 64 69 72 71 32 76 29 20 5c 20 6e 6f 74 20 |oldirq2v) \ not |
00003e60 54 54 58 20 69 6e 74 65 72 72 75 70 74 0d 20 20 |TTX interrupt. |
00003e70 38 32 30 20 2e 74 74 78 69 6e 74 65 72 0d 20 20 |820 .ttxinter. |
00003e80 38 33 30 20 20 20 20 20 20 20 20 20 4c 44 41 20 |830 LDA |
00003e90 73 61 76 65 72 65 67 20 20 20 5c 20 69 6e 74 65 |savereg \ inte|
00003ea0 72 72 75 70 74 20 61 63 63 75 6d 75 6c 61 74 6f |rrupt accumulato|
00003eb0 72 20 73 61 76 65 20 72 65 67 69 73 74 65 72 0d |r save register.|
00003ec0 20 20 38 34 30 20 20 20 20 20 20 20 20 20 50 48 | 840 PH|
00003ed0 41 20 20 20 20 20 20 20 20 20 20 20 5c 20 70 75 |A \ pu|
00003ee0 73 68 20 69 6e 74 65 72 72 75 70 74 20 61 63 63 |sh interrupt acc|
00003ef0 75 6d 75 6c 61 74 6f 72 20 73 61 76 65 20 72 65 |umulator save re|
00003f00 67 69 73 74 65 72 0d 20 20 38 35 30 20 20 20 20 |gister. 850 |
00003f10 20 20 20 20 20 54 58 41 0d 20 20 38 36 30 20 20 | TXA. 860 |
00003f20 20 20 20 20 20 20 20 50 48 41 20 20 20 20 20 20 | PHA |
00003f30 20 20 20 20 20 5c 20 70 75 73 68 20 58 0d 20 20 | \ push X. |
00003f40 38 37 30 20 20 20 20 20 20 20 20 20 54 59 41 0d |870 TYA.|
00003f50 20 20 38 38 30 20 20 20 20 20 20 20 20 20 50 48 | 880 PH|
00003f60 41 20 20 20 20 20 20 20 20 20 20 20 5c 20 70 75 |A \ pu|
00003f70 73 68 20 59 0d 20 20 38 39 30 20 20 20 20 20 20 |sh Y. 890 |
00003f80 20 20 20 53 45 44 0d 20 20 39 30 30 20 20 20 20 | SED. 900 |
00003f90 20 20 20 20 20 43 4c 43 0d 20 20 39 31 30 20 20 | CLC. 910 |
00003fa0 20 20 20 20 20 20 20 4c 44 41 20 23 26 30 31 0d | LDA #&01.|
00003fb0 20 20 39 32 30 20 20 20 20 20 20 20 20 20 41 44 | 920 AD|
00003fc0 43 20 63 6f 75 6e 74 65 72 20 20 20 5c 20 61 64 |C counter \ ad|
00003fd0 64 20 31 20 66 6f 72 20 65 76 65 72 79 20 54 54 |d 1 for every TT|
00003fe0 58 20 69 6e 74 65 72 72 75 70 74 0d 20 20 39 33 |X interrupt. 93|
00003ff0 30 20 20 20 20 20 20 20 20 20 53 54 41 20 63 6f |0 STA co|
00004000 75 6e 74 65 72 0d 20 20 39 34 30 20 20 20 20 20 |unter. 940 |
00004010 20 20 20 20 4c 44 41 20 23 26 30 30 0d 20 20 39 | LDA #&00. 9|
00004020 35 30 20 20 20 20 20 20 20 20 20 41 44 43 20 63 |50 ADC c|
00004030 6f 75 6e 74 65 72 2b 31 0d 20 20 39 36 30 20 20 |ounter+1. 960 |
00004040 20 20 20 20 20 20 20 53 54 41 20 63 6f 75 6e 74 | STA count|
00004050 65 72 2b 31 0d 20 20 39 37 30 20 20 20 20 20 20 |er+1. 970 |
00004060 20 20 20 4c 44 41 20 23 26 30 30 0d 20 20 39 38 | LDA #&00. 98|
00004070 30 20 20 20 20 20 20 20 20 20 41 44 43 20 63 6f |0 ADC co|
00004080 75 6e 74 65 72 2b 32 0d 20 20 39 39 30 20 20 20 |unter+2. 990 |
00004090 20 20 20 20 20 20 53 54 41 20 63 6f 75 6e 74 65 | STA counte|
000040a0 72 2b 32 0d 20 31 30 30 30 20 20 20 20 20 20 20 |r+2. 1000 |
000040b0 20 20 4c 44 41 20 23 26 30 30 0d 20 31 30 31 30 | LDA #&00. 1010|
000040c0 20 20 20 20 20 20 20 20 20 41 44 43 20 63 6f 75 | ADC cou|
000040d0 6e 74 65 72 2b 33 0d 20 31 30 32 30 20 20 20 20 |nter+3. 1020 |
000040e0 20 20 20 20 20 53 54 41 20 63 6f 75 6e 74 65 72 | STA counter|
000040f0 2b 33 0d 20 31 30 33 30 20 20 20 20 20 20 20 20 |+3. 1030 |
00004100 20 4c 44 41 20 23 26 30 30 0d 20 31 30 34 30 20 | LDA #&00. 1040 |
00004110 20 20 20 20 20 20 20 20 4c 44 59 20 23 26 30 46 | LDY #&0F|
00004120 20 20 20 20 20 20 5c 20 63 6c 65 61 72 20 31 36 | \ clear 16|
00004130 20 72 6f 77 73 20 69 6e 20 61 64 61 70 74 6f 72 | rows in adaptor|
00004140 0d 20 31 30 35 30 20 2e 63 6c 65 61 72 6c 6f 6f |. 1050 .clearloo|
00004150 70 0d 20 31 30 36 30 20 20 20 20 20 20 20 20 20 |p. 1060 |
00004160 53 54 59 20 72 6f 77 72 65 67 0d 20 31 30 37 30 |STY rowreg. 1070|
00004170 20 20 20 20 20 20 20 20 20 53 54 41 20 64 61 74 | STA dat|
00004180 61 72 65 67 0d 20 31 30 38 30 20 20 20 20 20 20 |areg. 1080 |
00004190 20 20 20 44 45 59 0d 20 31 30 39 30 20 20 20 20 | DEY. 1090 |
000041a0 20 20 20 20 20 42 50 4c 20 63 6c 65 61 72 6c 6f | BPL clearlo|
000041b0 6f 70 0d 20 31 31 30 30 20 20 20 20 20 20 20 20 |op. 1100 |
000041c0 20 53 54 41 20 73 74 61 74 63 6c 72 20 20 20 5c | STA statclr \|
000041d0 20 63 6c 65 61 72 20 73 74 61 74 75 73 20 66 6c | clear status fl|
000041e0 61 67 73 20 62 65 66 6f 72 65 20 72 65 74 75 72 |ags before retur|
000041f0 6e 69 6e 67 0d 20 31 31 31 30 20 20 20 20 20 20 |ning. 1110 |
00004200 20 20 20 50 4c 41 0d 20 31 31 32 30 20 20 20 20 | PLA. 1120 |
00004210 20 20 20 20 20 54 41 59 20 20 20 20 20 20 20 20 | TAY |
00004220 20 20 20 5c 20 72 65 73 74 6f 72 65 20 59 0d 20 | \ restore Y. |
00004230 31 31 33 30 20 20 20 20 20 20 20 20 20 50 4c 41 |1130 PLA|
00004240 0d 20 31 31 34 30 20 20 20 20 20 20 20 20 20 54 |. 1140 T|
00004250 41 58 20 20 20 20 20 20 20 20 20 20 20 5c 20 72 |AX \ r|
00004260 65 73 74 6f 72 65 20 58 0d 20 31 31 35 30 20 20 |estore X. 1150 |
00004270 20 20 20 20 20 20 20 50 4c 41 0d 20 31 31 36 30 | PLA. 1160|
00004280 20 20 20 20 20 20 20 20 20 53 54 41 20 73 61 76 | STA sav|
00004290 65 72 65 67 20 20 20 5c 20 72 65 73 74 6f 72 65 |ereg \ restore|
000042a0 20 69 6e 74 65 72 72 75 70 74 20 61 63 63 75 6d | interrupt accum|
000042b0 75 6c 61 74 6f 72 20 73 61 76 65 20 72 65 67 69 |ulator save regi|
000042c0 73 74 65 72 0d 20 31 31 37 30 20 20 20 20 20 20 |ster. 1170 |
000042d0 20 20 20 52 54 49 20 20 20 20 20 20 20 20 20 20 | RTI |
000042e0 20 5c 20 72 65 74 75 72 6e 20 66 72 6f 6d 20 69 | \ return from i|
000042f0 6e 74 65 72 72 75 70 74 0d 20 31 31 38 30 20 2e |nterrupt. 1180 .|
00004300 70 72 69 6e 74 62 63 64 0d 20 31 31 39 30 20 20 |printbcd. 1190 |
00004310 20 20 20 20 20 20 20 50 48 41 0d 20 31 32 30 30 | PHA. 1200|
00004320 20 20 20 20 20 20 20 20 20 4c 53 52 20 41 0d 20 | LSR A. |
00004330 31 32 31 30 20 20 20 20 20 20 20 20 20 4c 53 52 |1210 LSR|
00004340 20 41 0d 20 31 32 32 30 20 20 20 20 20 20 20 20 | A. 1220 |
00004350 20 4c 53 52 20 41 0d 20 31 32 33 30 20 20 20 20 | LSR A. 1230 |
00004360 20 20 20 20 20 4c 53 52 20 41 0d 20 31 32 34 30 | LSR A. 1240|
00004370 20 20 20 20 20 20 20 20 20 4a 53 52 20 6e 79 62 | JSR nyb|
00004380 62 6c 65 0d 20 31 32 35 30 20 20 20 20 20 20 20 |ble. 1250 |
00004390 20 20 50 4c 41 0d 20 31 32 36 30 20 2e 6e 79 62 | PLA. 1260 .nyb|
000043a0 62 6c 65 0d 20 31 32 37 30 20 20 20 20 20 20 20 |ble. 1270 |
000043b0 20 20 41 4e 44 20 23 26 30 46 20 20 20 20 20 20 | AND #&0F |
000043c0 5c 20 64 65 63 69 6d 61 6c 20 31 35 0d 20 31 32 |\ decimal 15. 12|
000043d0 38 30 20 20 20 20 20 20 20 20 20 53 45 44 0d 20 |80 SED. |
000043e0 31 32 39 30 20 20 20 20 20 20 20 20 20 43 4c 43 |1290 CLC|
000043f0 0d 20 31 33 30 30 20 20 20 20 20 20 20 20 20 41 |. 1300 A|
00004400 44 43 20 23 26 39 30 20 20 20 20 20 20 5c 20 64 |DC #&90 \ d|
00004410 65 63 69 6d 61 6c 20 31 34 34 0d 20 31 33 31 30 |ecimal 144. 1310|
00004420 20 20 20 20 20 20 20 20 20 41 44 43 20 23 26 34 | ADC #&4|
00004430 30 20 20 20 20 20 20 5c 20 64 65 63 69 6d 61 6c |0 \ decimal|
00004440 20 36 34 0d 20 31 33 32 30 20 20 20 20 20 20 20 | 64. 1320 |
00004450 20 20 43 4c 44 0d 20 31 33 33 30 20 20 20 20 20 | CLD. 1330 |
00004460 20 20 20 20 4a 4d 50 20 6f 73 77 72 63 68 0d 20 | JMP oswrch. |
00004470 31 33 34 30 20 2e 63 6f 75 6e 74 65 72 0d 20 31 |1340 .counter. 1|
00004480 33 35 30 20 20 20 20 20 20 20 20 20 45 51 55 44 |350 EQUD|
00004490 20 26 30 30 0d 20 31 33 36 30 20 2e 6f 6c 64 69 | &00. 1360 .oldi|
000044a0 72 71 32 76 0d 20 31 33 37 30 20 20 20 20 20 20 |rq2v. 1370 |
000044b0 20 20 20 45 51 55 57 20 26 30 30 0d 20 31 33 38 | EQUW &00. 138|
000044c0 30 20 5d 0d 20 31 33 39 30 20 4e 45 58 54 0d 20 |0 ]. 1390 NEXT. |
000044d0 31 34 30 30 20 45 4e 44 50 52 4f 43 0d |1400 ENDPROC.|
000044dd 
12-03-89/T\TTX01.m0
12-03-89/T\TTX01.m1
12-03-89/T\TTX01.m2
12-03-89/T\TTX01.m4
12-03-89/T\TTX01.m5
.