�> SPMOUSE
*� param &10 :�: Osword parameter block
&� mcode &100 :�: assemble at mcode
(,ioaddr=&A00 :�: address for machine code
2,xcoord=&80 :�: x coordinate, range 0-255
<,ycoord=&81 :�: y coordinate, range 0-255
F7savereg=&FC :�: interrupt accumulator save register
Puserv=&200 :�: user vector
Z+irq1v=&204 :�: primary interrupt vector
d!drb=&FE60 :�: data register B
n,ddrb=&FE62 :�: data direction register B
x-pcr=&FE6C :�: peripheral control register
�)ifr=&FE6D :�: interrupt flag register
�+ier=&FE6E :�: interrupt enable register
�osword=&FFF1
�osbyte=&FFF4
�� pass=4 � 6 � 2
�O%=mcode
�
P%=ioaddr
�
[OPT pass
�CMP #&00 \ is this *CODE?
�$BNE return \ return if not *CODE
�:LDX irq1v \ current primary interrupt vector, low byte
�=LDY irq1v+1 \ current primary interrupt vector, high byte
�,CPY #interrupt � 256 \ compare high byte

/BEQ disable \ restore old vector if altered

6STX oldirq1v \ save original irq1 vector, low byte

9STY oldirq1v+1 \ save original irq1 vector, high byte

"4LDX #interrupt � 256 \ new irq1 vector, low byte

,5LDY #interrupt � 256 \ new irq1 vector, high byte

6$SEI \ set interrupt disable flag

@+STX irq1v \ alter irq1 vector, low byte

J.STY irq1v+1 \ alter irq1 vector, high byte

T&CLI \ clear interrupt disable flag

^*LDA #&98 \ %10011000, ie. enable CB1/2

h'STA ier \ interrupt enable register

r)LDA pcr \ peripheral control register

|0� #&0F \ � with %00001111, ie clear bits 4-7

�4�A #&50 \ � with %01010000, ie. set bits 4 and 6

�BSTA pcr \ interrupt on +ve transition, CB2 input, DRB to clear

�LDA #0 \ user port input

�(STA ddrb \ data direction register B

�/STA xcoord \ initial value for x coordinate

�/STA ycoord \ initial value for y coordinate

�.return

�RTS \ return to BASIC

�.disable

�;LDA #&18 \ %00011000 ready to clear bits 3 and 4 of ier

�1LDX oldirq1v \ original irq1 vector, low byte

�4LDY oldirq1v+1 \ original irq1 vector, high byte

�$SEI \ set interrupt disable flag
'STA ier \ interrupt enable register
)LDA pcr \ peripheral control register
� #&0F \ clear bits 4-7
&)STA pcr \ peripheral control register
0:STX irq1v \ restore the original irq1 vector, low byte
:=STY irq1v+1 \ restore the original irq1 vector, high byte
D&CLI \ clear interrupt disable flag
NRTS \ return to BASIC
X.interrupt
b5LDA savereg \ interrupt accumulator save register
l"PHA \ and push it on the stack
v%LDA ifr \ interrupt flag register
�1BPL notuser \ bit 7 is set if VIA-B interrupt
�4� #&18 \ � with %00011000, ie. test bits 3 and 4
�(BEQ notuser \ exit if not CB1 or CB2
�-� #&10 \ � with %00010000, ie. test bit 4
�6BNE xpulse \ bit 4 set for an X direction movement
�/LDA drb \ Y direction, load data register B
�-� #&04 \ � with %00000100, ie. test bit 2
�4BNE ydown \ if bit 2 is set then Y is going down
�8INC ycoord \ Y is going up so increment Y coordinate
�.BNE exit \ branch if in the range 1 to 255
�(BEQ decy \ if zero then alter to 255
�
.ydown
�"LDA ycoord \ load Y coordinate
;BEQ exit \ branch if zero because it can't go any lower
	.decy
)DEC ycoord \ reduce Y coordinate by 1
 BJMP exit \ restore interrupt accumulator save register and RTI
*.xpulse
4"LDA drb \ load data register B
>ROR A \ bit 0 into carry
H/BCS xdown \ X is going down if bit 0 is set
R0INC xcoord \ X is going up if bit 0 is clear
\ABNE exit \ exit if X coordinate is in the range from 1 to 255
f3BEQ decx \ if X coordinate = 0 then make it 255
p
.xdown
z"LDA xcoord \ load X coordinate
�2BEQ exit \ if it is zero it can't go any lower
�	.decx
�+DEC xcoord \ decrease X coordinate by 1
�	.exit
�@PLA \ pull interrupt accumulator save register off the stack
�'STA savereg \ and restore zero page
�RTI \ return from interrupt
�.notuser
�DPLA \ pull the interrupt accumulator save register off the stack
�/STA savereg \ restore the zero page address
�1JMP (oldirq1v) \ exit via the original vector
�
.oldirq1v
�#EQUW &00 \ original irq1 vector

.lastbyte
]
�
$end=mcode+(lastbyte-ioaddr)
.addr=ioaddr
8� byte=mcode � end
B�write(?byte,addr)
Laddr=addr+1
V�
` �write((ioaddr � 256),userv)
j"�write((ioaddr � 256),userv+1)
t	*CODE
~�7
�Hmouse$=�141+�132+�157+�131+"Mouse coordinates, range &00-&FF  "+�156
��0,1)mouse$
��0,2)mouse$
�
� � �TJE
��23,1,0;0;0;0;
�.�10,7)"Bytes used = &";~(lastbyte-ioaddr)
��
�#�10,12)"X = &";~�read(&80);" "
�#�20,12)"Y = &";~�read(&81);" "
�.� �right �22,17)"Right" � �22,17)"     "
�1� �centre �15,17)"Centre" � �15,17)"      "
�+� �left �10,17)"Left" � �10,17)"    "
� �

	*CODE
�23,1,1;0;0;0;31,0,23
�
(��write(data,addr)
2!param=addr � &FFFF0000
<param?4=data
FA%=6
PX%=param � 256
ZY%=param � 256
d� osword
n�
xݤread(addr)
�!param=addr � &FFFF0000
�A%=5
�X%=param � 256
�Y%=param � 256
�� osword
�=param?4
�ݤbutton
�
A%=&96
�
X%=&60
�!=(�(osbyte) � &FF0000)�&10000
�ݤright
�=((�button � &80)=0)
�ݤcentre
=((�button � &40)=0)

ݤleft
=((�button � &20)=0)
�

00000000  0d 00 0a 0e f4 3e 20 53  50 4d 4f 55 53 45 0d 00  |.....> SPMOUSE..|
00000010  14 2a de 20 70 61 72 61  6d 20 26 31 30 20 3a f4  |.*. param &10 :.|
00000020  3a 20 4f 73 77 6f 72 64  20 70 61 72 61 6d 65 74  |: Osword paramet|
00000030  65 72 20 62 6c 6f 63 6b  0d 00 1e 26 de 20 6d 63  |er block...&. mc|
00000040  6f 64 65 20 26 31 30 30  20 3a f4 3a 20 61 73 73  |ode &100 :.: ass|
00000050  65 6d 62 6c 65 20 61 74  20 6d 63 6f 64 65 0d 00  |emble at mcode..|
00000060  28 2c 69 6f 61 64 64 72  3d 26 41 30 30 20 3a f4  |(,ioaddr=&A00 :.|
00000070  3a 20 61 64 64 72 65 73  73 20 66 6f 72 20 6d 61  |: address for ma|
00000080  63 68 69 6e 65 20 63 6f  64 65 0d 00 32 2c 78 63  |chine code..2,xc|
00000090  6f 6f 72 64 3d 26 38 30  20 3a f4 3a 20 78 20 63  |oord=&80 :.: x c|
000000a0  6f 6f 72 64 69 6e 61 74  65 2c 20 72 61 6e 67 65  |oordinate, range|
000000b0  20 30 2d 32 35 35 0d 00  3c 2c 79 63 6f 6f 72 64  | 0-255..<,ycoord|
000000c0  3d 26 38 31 20 3a f4 3a  20 79 20 63 6f 6f 72 64  |=&81 :.: y coord|
000000d0  69 6e 61 74 65 2c 20 72  61 6e 67 65 20 30 2d 32  |inate, range 0-2|
000000e0  35 35 0d 00 46 37 73 61  76 65 72 65 67 3d 26 46  |55..F7savereg=&F|
000000f0  43 20 3a f4 3a 20 69 6e  74 65 72 72 75 70 74 20  |C :.: interrupt |
00000100  61 63 63 75 6d 75 6c 61  74 6f 72 20 73 61 76 65  |accumulator save|
00000110  20 72 65 67 69 73 74 65  72 0d 00 50 1e 75 73 65  | register..P.use|
00000120  72 76 3d 26 32 30 30 20  3a f4 3a 20 75 73 65 72  |rv=&200 :.: user|
00000130  20 76 65 63 74 6f 72 0d  00 5a 2b 69 72 71 31 76  | vector..Z+irq1v|
00000140  3d 26 32 30 34 20 3a f4  3a 20 70 72 69 6d 61 72  |=&204 :.: primar|
00000150  79 20 69 6e 74 65 72 72  75 70 74 20 76 65 63 74  |y interrupt vect|
00000160  6f 72 0d 00 64 21 64 72  62 3d 26 46 45 36 30 20  |or..d!drb=&FE60 |
00000170  3a f4 3a 20 64 61 74 61  20 72 65 67 69 73 74 65  |:.: data registe|
00000180  72 20 42 0d 00 6e 2c 64  64 72 62 3d 26 46 45 36  |r B..n,ddrb=&FE6|
00000190  32 20 3a f4 3a 20 64 61  74 61 20 64 69 72 65 63  |2 :.: data direc|
000001a0  74 69 6f 6e 20 72 65 67  69 73 74 65 72 20 42 0d  |tion register B.|
000001b0  00 78 2d 70 63 72 3d 26  46 45 36 43 20 3a f4 3a  |.x-pcr=&FE6C :.:|
000001c0  20 70 65 72 69 70 68 65  72 61 6c 20 63 6f 6e 74  | peripheral cont|
000001d0  72 6f 6c 20 72 65 67 69  73 74 65 72 0d 00 82 29  |rol register...)|
000001e0  69 66 72 3d 26 46 45 36  44 20 3a f4 3a 20 69 6e  |ifr=&FE6D :.: in|
000001f0  74 65 72 72 75 70 74 20  66 6c 61 67 20 72 65 67  |terrupt flag reg|
00000200  69 73 74 65 72 0d 00 8c  2b 69 65 72 3d 26 46 45  |ister...+ier=&FE|
00000210  36 45 20 3a f4 3a 20 69  6e 74 65 72 72 75 70 74  |6E :.: interrupt|
00000220  20 65 6e 61 62 6c 65 20  72 65 67 69 73 74 65 72  | enable register|
00000230  0d 00 96 10 6f 73 77 6f  72 64 3d 26 46 46 46 31  |....osword=&FFF1|
00000240  0d 00 a0 10 6f 73 62 79  74 65 3d 26 46 46 46 34  |....osbyte=&FFF4|
00000250  0d 00 aa 14 e3 20 70 61  73 73 3d 34 20 b8 20 36  |..... pass=4 . 6|
00000260  20 88 20 32 0d 00 b4 0c  4f 25 3d 6d 63 6f 64 65  | . 2....O%=mcode|
00000270  0d 00 be 0d 50 25 3d 69  6f 61 64 64 72 0d 00 c8  |....P%=ioaddr...|
00000280  0d 5b 4f 50 54 20 70 61  73 73 0d 00 d2 1d 43 4d  |.[OPT pass....CM|
00000290  50 20 23 26 30 30 20 5c  20 69 73 20 74 68 69 73  |P #&00 \ is this|
000002a0  20 2a 43 4f 44 45 3f 0d  00 dc 24 42 4e 45 20 72  | *CODE?...$BNE r|
000002b0  65 74 75 72 6e 20 5c 20  72 65 74 75 72 6e 20 69  |eturn \ return i|
000002c0  66 20 6e 6f 74 20 2a 43  4f 44 45 0d 00 e6 3a 4c  |f not *CODE...:L|
000002d0  44 58 20 69 72 71 31 76  20 5c 20 63 75 72 72 65  |DX irq1v \ curre|
000002e0  6e 74 20 70 72 69 6d 61  72 79 20 69 6e 74 65 72  |nt primary inter|
000002f0  72 75 70 74 20 76 65 63  74 6f 72 2c 20 6c 6f 77  |rupt vector, low|
00000300  20 62 79 74 65 0d 00 f0  3d 4c 44 59 20 69 72 71  | byte...=LDY irq|
00000310  31 76 2b 31 20 5c 20 63  75 72 72 65 6e 74 20 70  |1v+1 \ current p|
00000320  72 69 6d 61 72 79 20 69  6e 74 65 72 72 75 70 74  |rimary interrupt|
00000330  20 76 65 63 74 6f 72 2c  20 68 69 67 68 20 62 79  | vector, high by|
00000340  74 65 0d 00 fa 2c 43 50  59 20 23 69 6e 74 65 72  |te...,CPY #inter|
00000350  72 75 70 74 20 81 20 32  35 36 20 5c 20 63 6f 6d  |rupt . 256 \ com|
00000360  70 61 72 65 20 68 69 67  68 20 62 79 74 65 0d 01  |pare high byte..|
00000370  04 2f 42 45 51 20 64 69  73 61 62 6c 65 20 5c 20  |./BEQ disable \ |
00000380  72 65 73 74 6f 72 65 20  6f 6c 64 20 76 65 63 74  |restore old vect|
00000390  6f 72 20 69 66 20 61 6c  74 65 72 65 64 0d 01 0e  |or if altered...|
000003a0  36 53 54 58 20 6f 6c 64  69 72 71 31 76 20 5c 20  |6STX oldirq1v \ |
000003b0  73 61 76 65 20 6f 72 69  67 69 6e 61 6c 20 69 72  |save original ir|
000003c0  71 31 20 76 65 63 74 6f  72 2c 20 6c 6f 77 20 62  |q1 vector, low b|
000003d0  79 74 65 0d 01 18 39 53  54 59 20 6f 6c 64 69 72  |yte...9STY oldir|
000003e0  71 31 76 2b 31 20 5c 20  73 61 76 65 20 6f 72 69  |q1v+1 \ save ori|
000003f0  67 69 6e 61 6c 20 69 72  71 31 20 76 65 63 74 6f  |ginal irq1 vecto|
00000400  72 2c 20 68 69 67 68 20  62 79 74 65 0d 01 22 34  |r, high byte.."4|
00000410  4c 44 58 20 23 69 6e 74  65 72 72 75 70 74 20 83  |LDX #interrupt .|
00000420  20 32 35 36 20 5c 20 6e  65 77 20 69 72 71 31 20  | 256 \ new irq1 |
00000430  76 65 63 74 6f 72 2c 20  6c 6f 77 20 62 79 74 65  |vector, low byte|
00000440  0d 01 2c 35 4c 44 59 20  23 69 6e 74 65 72 72 75  |..,5LDY #interru|
00000450  70 74 20 81 20 32 35 36  20 5c 20 6e 65 77 20 69  |pt . 256 \ new i|
00000460  72 71 31 20 76 65 63 74  6f 72 2c 20 68 69 67 68  |rq1 vector, high|
00000470  20 62 79 74 65 0d 01 36  24 53 45 49 20 5c 20 73  | byte..6$SEI \ s|
00000480  65 74 20 69 6e 74 65 72  72 75 70 74 20 64 69 73  |et interrupt dis|
00000490  61 62 6c 65 20 66 6c 61  67 0d 01 40 2b 53 54 58  |able flag..@+STX|
000004a0  20 69 72 71 31 76 20 5c  20 61 6c 74 65 72 20 69  | irq1v \ alter i|
000004b0  72 71 31 20 76 65 63 74  6f 72 2c 20 6c 6f 77 20  |rq1 vector, low |
000004c0  62 79 74 65 0d 01 4a 2e  53 54 59 20 69 72 71 31  |byte..J.STY irq1|
000004d0  76 2b 31 20 5c 20 61 6c  74 65 72 20 69 72 71 31  |v+1 \ alter irq1|
000004e0  20 76 65 63 74 6f 72 2c  20 68 69 67 68 20 62 79  | vector, high by|
000004f0  74 65 0d 01 54 26 43 4c  49 20 5c 20 63 6c 65 61  |te..T&CLI \ clea|
00000500  72 20 69 6e 74 65 72 72  75 70 74 20 64 69 73 61  |r interrupt disa|
00000510  62 6c 65 20 66 6c 61 67  0d 01 5e 2a 4c 44 41 20  |ble flag..^*LDA |
00000520  23 26 39 38 20 5c 20 25  31 30 30 31 31 30 30 30  |#&98 \ %10011000|
00000530  2c 20 69 65 2e 20 65 6e  61 62 6c 65 20 43 42 31  |, ie. enable CB1|
00000540  2f 32 0d 01 68 27 53 54  41 20 69 65 72 20 5c 20  |/2..h'STA ier \ |
00000550  69 6e 74 65 72 72 75 70  74 20 65 6e 61 62 6c 65  |interrupt enable|
00000560  20 72 65 67 69 73 74 65  72 0d 01 72 29 4c 44 41  | register..r)LDA|
00000570  20 70 63 72 20 5c 20 70  65 72 69 70 68 65 72 61  | pcr \ periphera|
00000580  6c 20 63 6f 6e 74 72 6f  6c 20 72 65 67 69 73 74  |l control regist|
00000590  65 72 0d 01 7c 30 80 20  23 26 30 46 20 5c 20 80  |er..|0. #&0F \ .|
000005a0  20 77 69 74 68 20 25 30  30 30 30 31 31 31 31 2c  | with %00001111,|
000005b0  20 69 65 20 63 6c 65 61  72 20 62 69 74 73 20 34  | ie clear bits 4|
000005c0  2d 37 0d 01 86 34 84 41  20 23 26 35 30 20 5c 20  |-7...4.A #&50 \ |
000005d0  84 20 77 69 74 68 20 25  30 31 30 31 30 30 30 30  |. with %01010000|
000005e0  2c 20 69 65 2e 20 73 65  74 20 62 69 74 73 20 34  |, ie. set bits 4|
000005f0  20 61 6e 64 20 36 0d 01  90 42 53 54 41 20 70 63  | and 6...BSTA pc|
00000600  72 20 5c 20 69 6e 74 65  72 72 75 70 74 20 6f 6e  |r \ interrupt on|
00000610  20 2b 76 65 20 74 72 61  6e 73 69 74 69 6f 6e 2c  | +ve transition,|
00000620  20 43 42 32 20 69 6e 70  75 74 2c 20 44 52 42 20  | CB2 input, DRB |
00000630  74 6f 20 63 6c 65 61 72  0d 01 9a 1c 4c 44 41 20  |to clear....LDA |
00000640  23 30 20 5c 20 75 73 65  72 20 70 6f 72 74 20 69  |#0 \ user port i|
00000650  6e 70 75 74 0d 01 a4 28  53 54 41 20 64 64 72 62  |nput...(STA ddrb|
00000660  20 5c 20 64 61 74 61 20  64 69 72 65 63 74 69 6f  | \ data directio|
00000670  6e 20 72 65 67 69 73 74  65 72 20 42 0d 01 ae 2f  |n register B.../|
00000680  53 54 41 20 78 63 6f 6f  72 64 20 5c 20 69 6e 69  |STA xcoord \ ini|
00000690  74 69 61 6c 20 76 61 6c  75 65 20 66 6f 72 20 78  |tial value for x|
000006a0  20 63 6f 6f 72 64 69 6e  61 74 65 0d 01 b8 2f 53  | coordinate.../S|
000006b0  54 41 20 79 63 6f 6f 72  64 20 5c 20 69 6e 69 74  |TA ycoord \ init|
000006c0  69 61 6c 20 76 61 6c 75  65 20 66 6f 72 20 79 20  |ial value for y |
000006d0  63 6f 6f 72 64 69 6e 61  74 65 0d 01 c2 0b 2e 72  |coordinate.....r|
000006e0  65 74 75 72 6e 0d 01 cc  19 52 54 53 20 5c 20 72  |eturn....RTS \ r|
000006f0  65 74 75 72 6e 20 74 6f  20 42 41 53 49 43 0d 01  |eturn to BASIC..|
00000700  d6 0c 2e 64 69 73 61 62  6c 65 0d 01 e0 3b 4c 44  |...disable...;LD|
00000710  41 20 23 26 31 38 20 5c  20 25 30 30 30 31 31 30  |A #&18 \ %000110|
00000720  30 30 20 72 65 61 64 79  20 74 6f 20 63 6c 65 61  |00 ready to clea|
00000730  72 20 62 69 74 73 20 33  20 61 6e 64 20 34 20 6f  |r bits 3 and 4 o|
00000740  66 20 69 65 72 0d 01 ea  31 4c 44 58 20 6f 6c 64  |f ier...1LDX old|
00000750  69 72 71 31 76 20 5c 20  6f 72 69 67 69 6e 61 6c  |irq1v \ original|
00000760  20 69 72 71 31 20 76 65  63 74 6f 72 2c 20 6c 6f  | irq1 vector, lo|
00000770  77 20 62 79 74 65 0d 01  f4 34 4c 44 59 20 6f 6c  |w byte...4LDY ol|
00000780  64 69 72 71 31 76 2b 31  20 5c 20 6f 72 69 67 69  |dirq1v+1 \ origi|
00000790  6e 61 6c 20 69 72 71 31  20 76 65 63 74 6f 72 2c  |nal irq1 vector,|
000007a0  20 68 69 67 68 20 62 79  74 65 0d 01 fe 24 53 45  | high byte...$SE|
000007b0  49 20 5c 20 73 65 74 20  69 6e 74 65 72 72 75 70  |I \ set interrup|
000007c0  74 20 64 69 73 61 62 6c  65 20 66 6c 61 67 0d 02  |t disable flag..|
000007d0  08 27 53 54 41 20 69 65  72 20 5c 20 69 6e 74 65  |.'STA ier \ inte|
000007e0  72 72 75 70 74 20 65 6e  61 62 6c 65 20 72 65 67  |rrupt enable reg|
000007f0  69 73 74 65 72 0d 02 12  29 4c 44 41 20 70 63 72  |ister...)LDA pcr|
00000800  20 5c 20 70 65 72 69 70  68 65 72 61 6c 20 63 6f  | \ peripheral co|
00000810  6e 74 72 6f 6c 20 72 65  67 69 73 74 65 72 0d 02  |ntrol register..|
00000820  1c 1b 80 20 23 26 30 46  20 5c 20 63 6c 65 61 72  |... #&0F \ clear|
00000830  20 62 69 74 73 20 34 2d  37 0d 02 26 29 53 54 41  | bits 4-7..&)STA|
00000840  20 70 63 72 20 5c 20 70  65 72 69 70 68 65 72 61  | pcr \ periphera|
00000850  6c 20 63 6f 6e 74 72 6f  6c 20 72 65 67 69 73 74  |l control regist|
00000860  65 72 0d 02 30 3a 53 54  58 20 69 72 71 31 76 20  |er..0:STX irq1v |
00000870  5c 20 72 65 73 74 6f 72  65 20 74 68 65 20 6f 72  |\ restore the or|
00000880  69 67 69 6e 61 6c 20 69  72 71 31 20 76 65 63 74  |iginal irq1 vect|
00000890  6f 72 2c 20 6c 6f 77 20  62 79 74 65 0d 02 3a 3d  |or, low byte..:=|
000008a0  53 54 59 20 69 72 71 31  76 2b 31 20 5c 20 72 65  |STY irq1v+1 \ re|
000008b0  73 74 6f 72 65 20 74 68  65 20 6f 72 69 67 69 6e  |store the origin|
000008c0  61 6c 20 69 72 71 31 20  76 65 63 74 6f 72 2c 20  |al irq1 vector, |
000008d0  68 69 67 68 20 62 79 74  65 0d 02 44 26 43 4c 49  |high byte..D&CLI|
000008e0  20 5c 20 63 6c 65 61 72  20 69 6e 74 65 72 72 75  | \ clear interru|
000008f0  70 74 20 64 69 73 61 62  6c 65 20 66 6c 61 67 0d  |pt disable flag.|
00000900  02 4e 19 52 54 53 20 5c  20 72 65 74 75 72 6e 20  |.N.RTS \ return |
00000910  74 6f 20 42 41 53 49 43  0d 02 58 0e 2e 69 6e 74  |to BASIC..X..int|
00000920  65 72 72 75 70 74 0d 02  62 35 4c 44 41 20 73 61  |errupt..b5LDA sa|
00000930  76 65 72 65 67 20 5c 20  69 6e 74 65 72 72 75 70  |vereg \ interrup|
00000940  74 20 61 63 63 75 6d 75  6c 61 74 6f 72 20 73 61  |t accumulator sa|
00000950  76 65 20 72 65 67 69 73  74 65 72 0d 02 6c 22 50  |ve register..l"P|
00000960  48 41 20 5c 20 61 6e 64  20 70 75 73 68 20 69 74  |HA \ and push it|
00000970  20 6f 6e 20 74 68 65 20  73 74 61 63 6b 0d 02 76  | on the stack..v|
00000980  25 4c 44 41 20 69 66 72  20 5c 20 69 6e 74 65 72  |%LDA ifr \ inter|
00000990  72 75 70 74 20 66 6c 61  67 20 72 65 67 69 73 74  |rupt flag regist|
000009a0  65 72 0d 02 80 31 42 50  4c 20 6e 6f 74 75 73 65  |er...1BPL notuse|
000009b0  72 20 5c 20 62 69 74 20  37 20 69 73 20 73 65 74  |r \ bit 7 is set|
000009c0  20 69 66 20 56 49 41 2d  42 20 69 6e 74 65 72 72  | if VIA-B interr|
000009d0  75 70 74 0d 02 8a 34 80  20 23 26 31 38 20 5c 20  |upt...4. #&18 \ |
000009e0  80 20 77 69 74 68 20 25  30 30 30 31 31 30 30 30  |. with %00011000|
000009f0  2c 20 69 65 2e 20 74 65  73 74 20 62 69 74 73 20  |, ie. test bits |
00000a00  33 20 61 6e 64 20 34 0d  02 94 28 42 45 51 20 6e  |3 and 4...(BEQ n|
00000a10  6f 74 75 73 65 72 20 5c  20 65 78 69 74 20 69 66  |otuser \ exit if|
00000a20  20 6e 6f 74 20 43 42 31  20 6f 72 20 43 42 32 0d  | not CB1 or CB2.|
00000a30  02 9e 2d 80 20 23 26 31  30 20 5c 20 80 20 77 69  |..-. #&10 \ . wi|
00000a40  74 68 20 25 30 30 30 31  30 30 30 30 2c 20 69 65  |th %00010000, ie|
00000a50  2e 20 74 65 73 74 20 62  69 74 20 34 0d 02 a8 36  |. test bit 4...6|
00000a60  42 4e 45 20 78 70 75 6c  73 65 20 5c 20 62 69 74  |BNE xpulse \ bit|
00000a70  20 34 20 73 65 74 20 66  6f 72 20 61 6e 20 58 20  | 4 set for an X |
00000a80  64 69 72 65 63 74 69 6f  6e 20 6d 6f 76 65 6d 65  |direction moveme|
00000a90  6e 74 0d 02 b2 2f 4c 44  41 20 64 72 62 20 5c 20  |nt.../LDA drb \ |
00000aa0  59 20 64 69 72 65 63 74  69 6f 6e 2c 20 6c 6f 61  |Y direction, loa|
00000ab0  64 20 64 61 74 61 20 72  65 67 69 73 74 65 72 20  |d data register |
00000ac0  42 0d 02 bc 2d 80 20 23  26 30 34 20 5c 20 80 20  |B...-. #&04 \ . |
00000ad0  77 69 74 68 20 25 30 30  30 30 30 31 30 30 2c 20  |with %00000100, |
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