Home » Archimedes archive » Acorn User » AU 1997-10 A.adf » Extras » Apple][e/PD/PIC/VUBars/ADCbasic
Apple][e/PD/PIC/VUBars/ADCbasic
This website contains an archive of files for the Acorn Electron, BBC Micro, Acorn Archimedes, Commodore 16 and Commodore 64 computers, which Dominic Ford has rescued from his private collection of floppy disks and cassettes.
Some of these files were originally commercial releases in the 1980s and 1990s, but they are now widely available online. I assume that copyright over them is no longer being asserted. If you own the copyright and would like files to be removed, please contact me.
| Tape/disk: | Home » Archimedes archive » Acorn User » AU 1997-10 A.adf » Extras |
| Filename: | Apple][e/PD/PIC/VUBars/ADCbasic |
| Read OK: | ✔ |
| File size: | 07EC bytes |
| Load address: | 0000 |
| Exec address: | 0000 |
File contents
10REM Read ADC0 and display result on bargraph connected to PB0-7 20REM Define some stuff 30INDADD=0 40RTCC=1 50PC=2 60STATUS=3:REM bit5 & bit6 are register page select 70FSR=4 80OPTREG=1:REM In bank 1 90ADCON0=8 100GO=2:REM Polled bit for ADC finished 110ADCON1=8:REM In bank 1 120ADRES=9 130PCLATH=10 140intcon=11 150CARRY=0:REM Carry bit 160DCARRY=1:REM Digit carry bit 170PDOWN=3:REM Power down bit 180WATDOG=4:REM Watchdog timeout bit 190W=0 200F=1 210Z=2 220SPARE=7:REM Unused status bit 230TEMP=12:REM Counter for ADC delay 240: 250PORTA=5 260PORTB=6 270TRISA=5:REM In bank 1 280TRISB=6:REM In bank 1 290BIT0=0 300BIT1=1 310BIT2=2 320BIT3=3 330BIT4=4 340BIT5=5 350BIT6=6 360BIT7=7:REM Text aliases 370: 380DIM code% 128 390FORX=3TO7STEP4 400P%=0:REM Reset vector for 16C71 410O%=code% 420[OPTX 430.init 440 CLRF PORTB \ Clear port B 450 BSF STATUS,BIT5 \ Forces registers to be R and W in page 1 460 MOVLW #0 470 MOVWF TRISB \ Set DDR to outputs 480 MOVLW #15 490 MOVWF TRISA \ Set DDR to inputs on bits 0 to 3 500 CLRF ADCON1 \ Use ADC0 and Vref=Vdd 510 BCF STATUS,BIT5 \ Read registers from page 0 again 520 MOVLW #193 530 MOVWF ADCON0 \ Set internal ADC clock running 540.main 550 BSF ADCON0,GO \ bit2 starts sample 560 MOVLW #&20 570 MOVWF TEMP 580.loop 590 DECFSZ TEMP,F 600 GOTO loop \ Waste 32 clock cycles 610.read 620 BTFSC ADCON0,GO 630 GOTO read \ Poll until complete 640 SWaPF ADRES,F 650 RRF ADRES,W 660 ANDLW #7 \ Get upper 3 bits only 670 CALL convert 680 MOVWF PORTB \ Write to LEDs 690 GOTO main 700.convert 710 ADDWF PC,F \ Look up table 720 RETLW #1 730 RETLW #2 740 RETLW #4 750 RETLW #8 760 RETLW #16 770 RETLW #32 780 RETLW #64 790 RETLW #128 800] 810NEXT
A� Read ADC0 and display result on bargraph connected to PB0-7
� Define some stuff
INDADD=0
(
RTCC=1
2PC=2
<4STATUS=3:� bit5 & bit6 are register page select
F FSR=4
POPTREG=1:� In bank 1
Z ADCON0=8
d'GO=2:� Polled bit for ADC finished
nADCON1=8:� In bank 1
x ADRES=9
�
PCLATH=10
�
intcon=11
�CARRY=0:� Carry bit
� DCARRY=1:� Digit carry bit
� PDOWN=3:� Power down bit
�$WATDOG=4:� Watchdog timeout bit
�W=0
�F=1
�Z=2
� SPARE=7:� Unused status bit
�#TEMP=12:� Counter for ADC delay
�:
� PORTA=5
PORTB=6
TRISA=5:� In bank 1
TRISB=6:� In bank 1
"
BIT0=0
,
BIT1=1
6
BIT2=2
@
BIT3=3
J
BIT4=4
T
BIT5=5
^
BIT6=6
hBIT7=7:� Text aliases
r:
|� code% 128
� �X=3�7�4
�!P%=0:� Reset vector for 16C71
� O%=code%
� [OPTX
� .init
�/ CLRF PORTB \ Clear port B
�K BSF STATUS,BIT5 \ Forces registers to be R and W in page 1
� MOVLW #0
�5 MOVWF TRISB \ Set DDR to outputs
� MOVLW #15
�C MOVWF TRISA \ Set DDR to inputs on bits 0 to 3
�8 CLRF ADCON1 \ Use ADC0 and Vref=Vdd
�C BCF STATUS,BIT5 \ Read registers from page 0 again
MOVLW #193
A MOVWF ADCON0 \ Set internal ADC clock running
.main
&5 BSF ADCON0,GO \ bit2 starts sample
0 MOVLW #&20
: MOVWF TEMP
D .loop
N DECFSZ TEMP,F
X5 � loop \ Waste 32 clock cycles
b .read
l BTFSC ADCON0,GO
v3 � read \ Poll until complete
� SWaPF ADRES,F
� RRF ADRES,W
�6 �LW #7 \ Get upper 3 bits only
� � convert
�0 MOVWF PORTB \ Write to LEDs
� � main
� .convert
�0 ADDWF PC,F \ Look up table
� RETLW #1
� RETLW #2
� RETLW #4
� RETLW #8
� RETLW #16
RETLW #32
RETLW #64
RETLW #128
]
*�
� 00000000 0d 00 0a 41 f4 20 52 65 61 64 20 41 44 43 30 20 |...A. Read ADC0 | 00000010 61 6e 64 20 64 69 73 70 6c 61 79 20 72 65 73 75 |and display resu| 00000020 6c 74 20 6f 6e 20 62 61 72 67 72 61 70 68 20 63 |lt on bargraph c| 00000030 6f 6e 6e 65 63 74 65 64 20 74 6f 20 50 42 30 2d |onnected to PB0-| 00000040 37 0d 00 14 17 f4 20 44 65 66 69 6e 65 20 73 6f |7..... Define so| 00000050 6d 65 20 73 74 75 66 66 0d 00 1e 0c 49 4e 44 41 |me stuff....INDA| 00000060 44 44 3d 30 0d 00 28 0a 52 54 43 43 3d 31 0d 00 |DD=0..(.RTCC=1..| 00000070 32 08 50 43 3d 32 0d 00 3c 34 53 54 41 54 55 53 |2.PC=2..<4STATUS| 00000080 3d 33 3a f4 20 20 62 69 74 35 20 26 20 62 69 74 |=3:. bit5 & bit| 00000090 36 20 61 72 65 20 72 65 67 69 73 74 65 72 20 70 |6 are register p| 000000a0 61 67 65 20 73 65 6c 65 63 74 0d 00 46 09 46 53 |age select..F.FS| 000000b0 52 3d 34 0d 00 50 19 4f 50 54 52 45 47 3d 31 3a |R=4..P.OPTREG=1:| 000000c0 f4 20 20 49 6e 20 62 61 6e 6b 20 31 0d 00 5a 0c |. In bank 1..Z.| 000000d0 41 44 43 4f 4e 30 3d 38 0d 00 64 27 47 4f 3d 32 |ADCON0=8..d'GO=2| 000000e0 3a f4 20 20 50 6f 6c 6c 65 64 20 62 69 74 20 66 |:. Polled bit f| 000000f0 6f 72 20 41 44 43 20 66 69 6e 69 73 68 65 64 0d |or ADC finished.| 00000100 00 6e 19 41 44 43 4f 4e 31 3d 38 3a f4 20 20 49 |.n.ADCON1=8:. I| 00000110 6e 20 62 61 6e 6b 20 31 0d 00 78 0b 41 44 52 45 |n bank 1..x.ADRE| 00000120 53 3d 39 0d 00 82 0d 50 43 4c 41 54 48 3d 31 30 |S=9....PCLATH=10| 00000130 0d 00 8c 0d 69 6e 74 63 6f 6e 3d 31 31 0d 00 96 |....intcon=11...| 00000140 18 43 41 52 52 59 3d 30 3a f4 20 20 43 61 72 72 |.CARRY=0:. Carr| 00000150 79 20 62 69 74 0d 00 a0 1f 44 43 41 52 52 59 3d |y bit....DCARRY=| 00000160 31 3a f4 20 20 44 69 67 69 74 20 63 61 72 72 79 |1:. Digit carry| 00000170 20 62 69 74 0d 00 aa 1d 50 44 4f 57 4e 3d 33 3a | bit....PDOWN=3:| 00000180 f4 20 20 50 6f 77 65 72 20 64 6f 77 6e 20 62 69 |. Power down bi| 00000190 74 0d 00 b4 24 57 41 54 44 4f 47 3d 34 3a f4 20 |t...$WATDOG=4:. | 000001a0 20 57 61 74 63 68 64 6f 67 20 74 69 6d 65 6f 75 | Watchdog timeou| 000001b0 74 20 62 69 74 0d 00 be 07 57 3d 30 0d 00 c8 07 |t bit....W=0....| 000001c0 46 3d 31 0d 00 d2 07 5a 3d 32 0d 00 dc 20 53 50 |F=1....Z=2... SP| 000001d0 41 52 45 3d 37 3a f4 20 20 55 6e 75 73 65 64 20 |ARE=7:. Unused | 000001e0 73 74 61 74 75 73 20 62 69 74 0d 00 e6 23 54 45 |status bit...#TE| 000001f0 4d 50 3d 31 32 3a f4 20 43 6f 75 6e 74 65 72 20 |MP=12:. Counter | 00000200 66 6f 72 20 41 44 43 20 64 65 6c 61 79 0d 00 f0 |for ADC delay...| 00000210 05 3a 0d 00 fa 0b 50 4f 52 54 41 3d 35 0d 01 04 |.:....PORTA=5...| 00000220 0b 50 4f 52 54 42 3d 36 0d 01 0e 18 54 52 49 53 |.PORTB=6....TRIS| 00000230 41 3d 35 3a f4 20 20 49 6e 20 62 61 6e 6b 20 31 |A=5:. In bank 1| 00000240 0d 01 18 18 54 52 49 53 42 3d 36 3a f4 20 20 49 |....TRISB=6:. I| 00000250 6e 20 62 61 6e 6b 20 31 0d 01 22 0a 42 49 54 30 |n bank 1..".BIT0| 00000260 3d 30 0d 01 2c 0a 42 49 54 31 3d 31 0d 01 36 0a |=0..,.BIT1=1..6.| 00000270 42 49 54 32 3d 32 0d 01 40 0a 42 49 54 33 3d 33 |BIT2=2..@.BIT3=3| 00000280 0d 01 4a 0a 42 49 54 34 3d 34 0d 01 54 0a 42 49 |..J.BIT4=4..T.BI| 00000290 54 35 3d 35 0d 01 5e 0a 42 49 54 36 3d 36 0d 01 |T5=5..^.BIT6=6..| 000002a0 68 1a 42 49 54 37 3d 37 3a f4 20 20 54 65 78 74 |h.BIT7=7:. Text| 000002b0 20 61 6c 69 61 73 65 73 0d 01 72 05 3a 0d 01 7c | aliases..r.:..|| 000002c0 0f de 20 63 6f 64 65 25 20 31 32 38 0d 01 86 0c |.. code% 128....| 000002d0 e3 58 3d 33 b8 37 88 34 0d 01 90 21 50 25 3d 30 |.X=3.7.4...!P%=0| 000002e0 3a f4 20 52 65 73 65 74 20 76 65 63 74 6f 72 20 |:. Reset vector | 000002f0 66 6f 72 20 31 36 43 37 31 0d 01 9a 0c 4f 25 3d |for 16C71....O%=| 00000300 63 6f 64 65 25 0d 01 a4 09 5b 4f 50 54 58 0d 01 |code%....[OPTX..| 00000310 ae 09 2e 69 6e 69 74 0d 01 b8 2f 20 20 20 20 20 |...init.../ | 00000320 20 20 20 20 20 43 4c 52 46 20 50 4f 52 54 42 20 | CLRF PORTB | 00000330 20 20 20 20 20 20 20 20 5c 20 43 6c 65 61 72 20 | \ Clear | 00000340 70 6f 72 74 20 42 0d 01 c2 4b 20 20 20 20 20 20 |port B...K | 00000350 20 20 20 20 42 53 46 20 53 54 41 54 55 53 2c 42 | BSF STATUS,B| 00000360 49 54 35 20 20 20 20 5c 20 46 6f 72 63 65 73 20 |IT5 \ Forces | 00000370 72 65 67 69 73 74 65 72 73 20 74 6f 20 62 65 20 |registers to be | 00000380 52 20 61 6e 64 20 57 20 69 6e 20 70 61 67 65 20 |R and W in page | 00000390 31 0d 01 cc 16 20 20 20 20 20 20 20 20 20 20 4d |1.... M| 000003a0 4f 56 4c 57 20 23 30 0d 01 d6 35 20 20 20 20 20 |OVLW #0...5 | 000003b0 20 20 20 20 20 4d 4f 56 57 46 20 54 52 49 53 42 | MOVWF TRISB| 000003c0 20 20 20 20 20 20 20 20 5c 20 53 65 74 20 44 44 | \ Set DD| 000003d0 52 20 74 6f 20 6f 75 74 70 75 74 73 0d 01 e0 17 |R to outputs....| 000003e0 20 20 20 20 20 20 20 20 20 20 4d 4f 56 4c 57 20 | MOVLW | 000003f0 23 31 35 0d 01 ea 43 20 20 20 20 20 20 20 20 20 |#15...C | 00000400 20 4d 4f 56 57 46 20 54 52 49 53 41 20 20 20 20 | MOVWF TRISA | 00000410 20 20 20 20 5c 20 53 65 74 20 44 44 52 20 74 6f | \ Set DDR to| 00000420 20 69 6e 70 75 74 73 20 6f 6e 20 62 69 74 73 20 | inputs on bits | 00000430 30 20 74 6f 20 33 0d 01 f4 38 20 20 20 20 20 20 |0 to 3...8 | 00000440 20 20 20 20 43 4c 52 46 20 41 44 43 4f 4e 31 20 | CLRF ADCON1 | 00000450 20 20 20 20 20 20 20 5c 20 55 73 65 20 41 44 43 | \ Use ADC| 00000460 30 20 61 6e 64 20 56 72 65 66 3d 56 64 64 0d 01 |0 and Vref=Vdd..| 00000470 fe 43 20 20 20 20 20 20 20 20 20 20 42 43 46 20 |.C BCF | 00000480 53 54 41 54 55 53 2c 42 49 54 35 20 20 20 20 5c |STATUS,BIT5 \| 00000490 20 52 65 61 64 20 72 65 67 69 73 74 65 72 73 20 | Read registers | 000004a0 66 72 6f 6d 20 70 61 67 65 20 30 20 61 67 61 69 |from page 0 agai| 000004b0 6e 0d 02 08 18 20 20 20 20 20 20 20 20 20 20 4d |n.... M| 000004c0 4f 56 4c 57 20 23 31 39 33 0d 02 12 41 20 20 20 |OVLW #193...A | 000004d0 20 20 20 20 20 20 20 4d 4f 56 57 46 20 41 44 43 | MOVWF ADC| 000004e0 4f 4e 30 20 20 20 20 20 20 20 5c 20 53 65 74 20 |ON0 \ Set | 000004f0 69 6e 74 65 72 6e 61 6c 20 41 44 43 20 63 6c 6f |internal ADC clo| 00000500 63 6b 20 72 75 6e 6e 69 6e 67 0d 02 1c 09 2e 6d |ck running.....m| 00000510 61 69 6e 0d 02 26 35 20 20 20 20 20 20 20 20 20 |ain..&5 | 00000520 20 42 53 46 20 41 44 43 4f 4e 30 2c 47 4f 20 20 | BSF ADCON0,GO | 00000530 20 20 20 20 5c 20 62 69 74 32 20 73 74 61 72 74 | \ bit2 start| 00000540 73 20 73 61 6d 70 6c 65 0d 02 30 18 20 20 20 20 |s sample..0. | 00000550 20 20 20 20 20 20 4d 4f 56 4c 57 20 23 26 32 30 | MOVLW #&20| 00000560 0d 02 3a 18 20 20 20 20 20 20 20 20 20 20 4d 4f |..:. MO| 00000570 56 57 46 20 54 45 4d 50 0d 02 44 09 2e 6c 6f 6f |VWF TEMP..D..loo| 00000580 70 0d 02 4e 1b 20 20 20 20 20 20 20 20 20 20 44 |p..N. D| 00000590 45 43 46 53 5a 20 54 45 4d 50 2c 46 0d 02 58 35 |ECFSZ TEMP,F..X5| 000005a0 20 20 20 20 20 20 20 20 20 20 e5 20 6c 6f 6f 70 | . loop| 000005b0 20 20 20 20 20 20 20 20 20 20 5c 20 57 61 73 74 | \ Wast| 000005c0 65 20 33 32 20 63 6c 6f 63 6b 20 63 79 63 6c 65 |e 32 clock cycle| 000005d0 73 0d 02 62 09 2e 72 65 61 64 0d 02 6c 1d 20 20 |s..b..read..l. | 000005e0 20 20 20 20 20 20 20 20 42 54 46 53 43 20 41 44 | BTFSC AD| 000005f0 43 4f 4e 30 2c 47 4f 0d 02 76 33 20 20 20 20 20 |CON0,GO..v3 | 00000600 20 20 20 20 20 e5 20 72 65 61 64 20 20 20 20 20 | . read | 00000610 20 20 20 20 20 5c 20 50 6f 6c 6c 20 75 6e 74 69 | \ Poll unti| 00000620 6c 20 63 6f 6d 70 6c 65 74 65 0d 02 80 1b 20 20 |l complete.... | 00000630 20 20 20 20 20 20 20 20 53 57 61 50 46 20 41 44 | SWaPF AD| 00000640 52 45 53 2c 46 0d 02 8a 19 20 20 20 20 20 20 20 |RES,F.... | 00000650 20 20 20 52 52 46 20 41 44 52 45 53 2c 57 0d 02 | RRF ADRES,W..| 00000660 94 36 20 20 20 20 20 20 20 20 20 20 80 4c 57 20 |.6 .LW | 00000670 23 37 20 20 20 20 20 20 20 20 20 20 20 5c 20 47 |#7 \ G| 00000680 65 74 20 75 70 70 65 72 20 33 20 62 69 74 73 20 |et upper 3 bits | 00000690 6f 6e 6c 79 0d 02 9e 17 20 20 20 20 20 20 20 20 |only.... | 000006a0 20 20 d6 20 63 6f 6e 76 65 72 74 0d 02 a8 30 20 | . convert...0 | 000006b0 20 20 20 20 20 20 20 20 20 4d 4f 56 57 46 20 50 | MOVWF P| 000006c0 4f 52 54 42 20 20 20 20 20 20 20 20 5c 20 57 72 |ORTB \ Wr| 000006d0 69 74 65 20 74 6f 20 4c 45 44 73 0d 02 b2 14 20 |ite to LEDs.... | 000006e0 20 20 20 20 20 20 20 20 20 e5 20 6d 61 69 6e 0d | . main.| 000006f0 02 bc 0c 2e 63 6f 6e 76 65 72 74 0d 02 c6 30 20 |....convert...0 | 00000700 20 20 20 20 20 20 20 20 20 41 44 44 57 46 20 50 | ADDWF P| 00000710 43 2c 46 20 20 20 20 20 20 20 20 20 5c 20 4c 6f |C,F \ Lo| 00000720 6f 6b 20 75 70 20 74 61 62 6c 65 0d 02 d0 16 20 |ok up table.... | 00000730 20 20 20 20 20 20 20 20 20 52 45 54 4c 57 20 23 | RETLW #| 00000740 31 0d 02 da 16 20 20 20 20 20 20 20 20 20 20 52 |1.... R| 00000750 45 54 4c 57 20 23 32 0d 02 e4 16 20 20 20 20 20 |ETLW #2.... | 00000760 20 20 20 20 20 52 45 54 4c 57 20 23 34 0d 02 ee | RETLW #4...| 00000770 16 20 20 20 20 20 20 20 20 20 20 52 45 54 4c 57 |. RETLW| 00000780 20 23 38 0d 02 f8 17 20 20 20 20 20 20 20 20 20 | #8.... | 00000790 20 52 45 54 4c 57 20 23 31 36 0d 03 02 17 20 20 | RETLW #16.... | 000007a0 20 20 20 20 20 20 20 20 52 45 54 4c 57 20 23 33 | RETLW #3| 000007b0 32 0d 03 0c 17 20 20 20 20 20 20 20 20 20 20 52 |2.... R| 000007c0 45 54 4c 57 20 23 36 34 0d 03 16 18 20 20 20 20 |ETLW #64.... | 000007d0 20 20 20 20 20 20 52 45 54 4c 57 20 23 31 32 38 | RETLW #128| 000007e0 0d 03 20 05 5d 0d 03 2a 05 ed 0d ff |.. .]..*....| 000007ec
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