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!Manuals/Assembly2

This website contains an archive of files for the Acorn Electron, BBC Micro, Acorn Archimedes, Commodore 16 and Commodore 64 computers, which Dominic Ford has rescued from his private collection of floppy disks and cassettes.

Some of these files were originally commercial releases in the 1980s and 1990s, but they are now widely available online. I assume that copyright over them is no longer being asserted. If you own the copyright and would like files to be removed, please contact me.

Tape/disk: Home » Archimedes archive » Acorn User » AU 1997-Xmas A.adf » StrongHelp
Filename: !Manuals/Assembly2
Read OK: ✔
File size: AB38 bytes
Load address: 0000
Exec address: 0000
File contents
HELP(�`�,���D$DIR$LLxF���p-��!!Root�
F���3�,��condtF���=�y�Op2XF������y�Rd�F���[ũy�Rn�F���'�y�S\F���ͩy�Shift F���!�vYADC|F����vADD�F����!vRSB�F����lv�SBC�F����(v�SUB� F����$v�RSC@#F����vNMOV�%F����v�MVN8(F����Iv�CMP�+F����vCMN/F���@vAND 1F����vDEORd3F���vrORR�5F���cv�BICd9F����voTST�<F�����vTEQ�?F�����vkMLADCF����v�MULFF�����v�SWI�HF���QY�vGBKF������y�BL�OF������y�LDR�QF�����ySTR�SF���@V�y6Byte�TF���0?�y�PC_rel�WF���d��ycPost [F����b�y!PreD^F���	�yRwb�bF���4H�y�LDMhF���OC�y�STM�mF���X/�y�M_opts�sF���ɣ�y�M_wbtxF�����y�stacks��F����v�yxstacks2t�F���Q��y�EQU\�F����x�yL%x�F���#��yOPT|�F���T�yWP%ԐF���C	�y0Reserve�F����)<z�ADR�F����b;z_ALIGNd�F���(�<zPassB_M��F����=z�usrH�F����N[z�P��G����LfqR14��G���]lf>R15��F���,�u}XCALL�F���v#��zCreditsDATA!Assembly
#background wimp 1
#wrap off
#align centre
*ARM Instructions*
#align
#tab
<ADC>	Add with Carry		<MUL>	Multiply
<ADD>	Add			<MVN>	Move Negative
<AND>	And			<ORR>	Inclusive OR
<B>	Branch			<RSB>	Reverse Subtract
<BIC>	Bit Clear		<RSC>	Reverse Subtract with Carry
<BL>	Branch with Link	<SBC>	Subtract with Carry
<CMN>	Compare Negative	<STM>	Store Multiple
<CMP>	Compare			<STR>	Store Register
<EOR>	Exclusive OR		<SUB>	Subtract
<LDM>	Load Multiple		<SWI>	Software Interrupt
<LDR>	Load Register		<TEQ>	Test for Equality
<MLA>	Multiply with Accumulate	<TST>	Test Masked	
<MOV>	Move			
#tab
#line
#align centre
*Registers*, *Integer Variables and Suffixes*
<Condition codes=>cond>    < Rd >    < Rn >    < Op2 >    <R14>    <R15>
<P%>    <L%>    < S >    < B =>Byte>    < P >
#line
*Pseudo opcodes*, *Assembler directives and CALL*
<OPT>    <EQU>    <ALIGN>    <ADR>    <CALL>
#line
*Miscellaneous*
<Reserving memory=>Reserve>
<Passing data to machine code routines=>PassB_M>
<Returning data to BASIC=>usr>
#line
<Credits and Copyright=>Credits>
DATA�Condition codes
#background wimp 1
All instructions are conditionally executed. If the condition in the top four bits of the instruction is not met, then even illegal instructions will have no effect...

#wrap off; tab
Condition field	 	 	Execute IF
#Line
  0000	EQ	:	 Z		(equal)
  0001	NE	:	~Z		(not equal)
  0010	CS	:	 C		(unsigned higher or same)
  0011	CC	:	~C		(unsigned lower)
  0100	MI	:	 N		(negative)
  0101	PL	:	~N		(positive or zero)
  0110	VS	:	 V		(overflow)
  0111	VC	:	~V		(no overflow)
  1000	HI	:	 C and ~Z	(unsigned higher)
  1001	LS	:	~C or Z		(unsigned lower or same)
  1010	GE	:	 N = V		(signed higher or same)
  1011	LT	:	 N \<\> V	(signed lower)
  1100	GT	:	~Z and (N = V)	(signed higher)
  1101	LE	:	 Z or (N \<\> V)	(signed lower or same)
  1110	AL	:	 1		(always)
  1111	NV	:	 0		(never)
#tab; wrap nojoin

( 1 is true, 0 is false, ~ is NOT )

Note: The NV code shouldn't be used anymore. If you want a no-op, you should use something like MOV R0,R0DATA�Op2
#background wimp 1
#wrap off
This can take several forms :
   -	Reg
   -	Reg <shift> #constant
   -	Reg <shift> Reg
	(Note: This takes an extra clock cycle)
   -	#constant
	( of the form Byte ROR n*2, n is 0..15 )DATA�Rd
#background wimp 1
Rd can be any of the registers from R0 to R15. If Rd = R15 then only the PC bits will be set, not the flags.DATA�Rn
#background wimp 1
Rn can be any of the registers from R0 to R15. If Rn = R15 then only the PC bits are used. The flag bits will appear cleared.DATA�The Status flag
#background wimp 1
Flags will only be updated if this is present. The S flag is implicit in CMP, CMN, TEQ and TST
#wrap off

  SUBS R1,R1,R2		;
  ADD  R1,R1,R3		; 
  Beq  xxx		; jump if R1-R2 = 0DATA�Shift
#background wimp 1
The shift types are :
  LSL	Logical Shift Left (*2)
  LSR	Logical Shift Right (/2)
  ASR	Arithmetic Shift Right (/2)
  ROR	ROtate Right
  RRX	Rotate Right eXtended

In all cases, the bit lost from the end is shifted into the carry flag. In ASR, the arithmetic sign of the number is preserved (+ve/-ve). In ROR, the bit lost is also copied back to bit 31. RRX is similar, but this time the carry flag acts as 'bit 32'.DATAYADC: Add with Carry
#background wimp 1
#wrap off
Syntax: ADC \{\<suffix\>\} \<destination\>, \<operand1\>, \<operand2\>
Operation: destination = operand one + operand two + carry
Flags: N,Z,C,V
#wrap on
#line
This operation performs the arithmetic addition of its two operands, also adding the carry flag. If set, the carry flag it is treated as one in the addition. (Otherwise, as zero). The result is stored in the destination register.
#line
ADC allows us to add together numbers which require more than a single word to represent them. e.g.
#tab
#indent 2
ADDS result_low, low1, low2	Add low words
ADCS result_high, high1, high2	Add high words + carry
#indent
#tab
*Note*: It is vital that the S suffix is used with these instructions, otherwise the carry flag setting will not be affected and will not be carried forward into the next addition.DATAADD: Add
#background wimp 1
#wrap off
Syntax: ADD \{\<suffix\>\} \<destination\>, \<operand1\>, \<operand2\>
Operation: destination = operand one + operand two
Flags: N,Z,C,V
#wrap on
#line
This instruction performs the arithmetic addition of its two operands, and stores the result in the destination register.
#line
Examples:
#Indent 2
ADD	R0,R3,R4	R0 = R3 + R4
ADDS	R0,R3,#2	R0 = R3 + 2 (Setting status flags)
ADDMI	R0,R0,#1	If minus flag set increment R0 by 1
ADD	R0,R0,R0,LSL#1	R0 = R0 + 2*R0  (R0 = 3*R0)
#IndentDATARSB: Reverse Subtract
#background wimp 1
#wrap off
Syntax: RSB \{\<suffix\>\} \<destination\>, \<operand1\>, \<operand2\>
Operation: destination = operand two - operand one
Flags: N,Z,C,V
#wrap on
#line
This instruction performs the arithmetic subtraction of its first operand from its second operand, and stores the result in the destination register. It is very similar to <SUB>.
#line
This is not a waste of an instruction! Operand two can be specified in several different formats, and it is thus much more flexible than operand one. The RSB instruction thus ensures that either of the operands used can be specified using the flexible format allowed by operand two.
#line
Examples:
#Indent 2
RSB	R0,R0,#0	R0 = 0 - R0 (R0 = -R0)
RSB	R6,R3,R7,LSL#2	R6 = (R7*4) - R3
#IndentDATA�SBC: Subtract with Carry
#background wimp 1
#wrap off
Syntax: SBC \{\<suffix\>\} \<destination\>, \<operand1\>, \<operand2\>
Operation: destination = operand one - operand two - not (carry)
Flags: N,Z,C,V
#wrap on
#line
This operation allows multi-word subtraction to be performed in the same way that <ADC> allows multi-word addition. This time the carry flag is used to indicate that a "borrow" occured when subtracting two words.
#line
SBC can be used for multi-word subtractions as follows:
#tab
#indent 2
SUBS result_low, low1, low2	Subtract low words
SBCS result_high, high1, high2	Subtract high words + carry
#indent
#tab
*Note*: It is vital that the S suffix is used to allow the subtract instructions to affect the carry flag.DATA�SUB: Subtract
#background wimp 1
#wrap off
Syntax: SUB \{\<suffix\>\} \<destination\>, \<operand1\>, \<operand2\>
Operation: destination = operand one - operand two
Flags: N,Z,C,V
#wrap on
#line
This instruction performs the arithmetic subtraction of its second operand from its first operand, and stores the result in the destination register.
#line
Examples:
#Indent 2
SUB	R10,R2,R4	R10 = R2 - R4
SUBMI	R1,R3,#1024	If neg flag set R1 = R3 - 1024
SUB	R0,R0,R0,LSL#1	R0 = R0 - 2*R0 (R0 = -R0)
#IndentDATA�RSC: Reverse Subtract with Carry
#background wimp 1
#wrap off
Syntax: RSC \{\<suffix\>\} \<destination\>, \<operand1\>, \<operand2\>
Operation: destination = operand two - operand one - not (carry)
Flags: N,Z,C,V
#wrap on
#line
This operation performs a reverse subtract operation while taking account of a previous borrow in the carry flag.
#line
This operand allows reversed subtraction to be performed on multi-word operands. It corresponds to the <SBC> instruction in the same way that <RSB> corresponds to <SUB>.
#line
Examples:
#wrap off
#Indent 2
RSBS	result_low, low1, low2		Reverse subtract low words
RSCS	result_high, high1, high2	Reverse subtract high words + carry
#Indent
#wrap onDATANMOV: Move Data
#background wimp 1
#wrap off
Syntax: MOV \{\<suffix\>\} \<destination\>, \<operand2\>
Operation: destination = operand two
Flags: N,Z,(C)
#wrap on
#line
This instruction moves data into the destination register. Operand two, as expected, can be specified as a register, an immediate operand or as a shifted register.
#line
Examples:
#wrap off
#Indent 2
MOV	R12,R0		Move the contents of R0 into R12
MOV	R6,R6,ASL#2	R6 = R6*4
MOV	R0,R2,ASL R5	R0 = R2 * (2^R5)
MOVEQS	R0,R4		If Z flag set Then R0 = R4 (setting flags)
MOV	R15,R14		Return from subroutine
#Indent
#wrap onDATA�MVN: Move Inverted Data
#background wimp 1
#wrap off
Syntax: MVN \{\<suffix\>\} \<destination\>, \<operand2\>
Operation: destination = not (operand two)
Flags: N,Z,(C)
#wrap on
#line
This instruction has exactly th same effect as <MOV>, except that all the bits moved from the source register are automatically inverted. This allows negative immediate numbers to be moved into registers
#line
Under the two's complement scheme, the number 'n' is represented as:
#Indent 4
NOT (n) + 1
#Indent
#line
Examples:
#wrap off
#Indent 2
MVN	R0,#0		Move -1 into register R0
MVN	R1,#9		Move -10 into R1
MVN	R3,R5		R3 = not (R5)
MVN	R6,R7,LSR #1	R6 = not (R7 div 2)
#Indent
#wrap onDATA�CMP: Compare
#background wimp 1
#wrap off
Syntax: CMP \{\<suffix\>\} \<operand1\>, \<operand2\>
Operation: Reflect result of operand one - operand two
Flags: N,Z,C,V
#wrap on
#line
This is a very important instruction connected with conditional instruction execution. The instruction compares two operands, and alters the status flags depending on the result.
#line
The result of the operation is not stored anywhere, which explains why there is no need for a destination field. The only thing to remember is that the various subsequent condition codes refer to operand one compared with operand two. Thus, the LT (less than) suffix will execute if operand one is less than operand two.
#line
Example:
#wrap off
#indent 2
CMP	R0,R1		Compare R0 with R1
SWIEQ	"OS_NewLine"	If (R0 - R1 = 0) execute SWI command
#indent
#wrap on
*Note*: Since the purpose of the CMP instruction is to affect the status flags, the S suffix does not have to be used.
DATACMN: Compare Negative
#background wimp 1
#wrap off
Syntax: CMN \{\<suffix\>\} \<operand1\>, \<operand2\>
Operation: Reflect result of operand one - (- operand two)
Flags: N,Z,C,V
#wrap on
#line
CMN is exactly the same as <CMP>, except that it compares operand one with the negative of operand two.
#line
This instruction allows comparisons to be made with small immediate constants which could not be represented otherwise. The ARM will automatically form the negative of operand two and then make the comparison.
#line
Examples
#wrap off
#indent 2
CMN	R5,R7		Compare R5 with -R7
CMN	R6,#1		Compare R6 with -1
CMN	R3,R0,LSL#1	Compare R3 with -R0*2
#indent
#wrap on
*Note*: Since the purpose of the CMP instruction is to affect the status flags, the S suffix does not have to be used.
DATAAND: Logical AND
#background wimp 1
#wrap off
Syntax: AND \{\<suffix\>\} \<destination\>, \<operand1\>, \<operand2\>
Operation: destination = operand one AND operand two
Flags: N,Z,(C)
#wrap on
#line
This operation performs a logical bitwise AND operation between its two operands, with the result being placed in the destination register.
#line
Examples:
#wrap off
#Indent 2
AND 	R0,R1,R2	R0 = R1 AND R2
AND	R5,R5,#%1111	R5 = R5 AND %1111 (clear all but low 4 bits)
ANDS	R4,R4,#1	R4 = R4 AND 1 (setting flags)
#Indent
#wrap onDATADEOR: Logical Exclusive OR
#background wimp 1
#wrap off
Syntax: EOR \{\<suffix\>\} \<destination\>, \<operand1\>, \<operand2\>
Operation: destination = operand one EOR operand two
Flags: N,Z,(C)
#wrap on
#line
This operation performs a logical bitwise EOR operation between its two operands, with the result being placed in the destination register.
#line
*Note*: EOR is very useful in 'toggling' data between two pre-defined values. For example, the register R0 can be toggled between 65 and 90 by EORing its contents with 27:
#Indent 4
.loop
EOR R0,R0,#27
B loop
#Indent
DATArORR: Logical OR
#background wimp 1
#wrap off
Syntax: ORR \{\<suffix\>\} \<destination\>, \<operand1\>, \<operand2\>
Operation: destination = operand one OR operand two
Flags: N,Z,(C)
#wrap on
#line
This instruction performs a logical bitwise OR operation between its two operands, with the result being placed in the destination register.
#line
*Note*: This operation is particularly useful for forcing certain bits to be set in a data word.
#line
Examples:
#wrap off
#Indent 2
ORR	R0,R11,R2	R0 = R11 OR R2
ORR	R7,R7,#%1100	R7 = R7 OR %1100 (set bits 2 & 3)
ORRS	R5,R5,#2	R5 = R5 OR #2 (setting flags)
#Indent
#wrap onDATA�BIC: Bit Clear
#background wimp 1
#wrap off
Syntax: BIC \{\<suffix\>\} \<destination\>, \<operand1\>, \<operand2\>
Operation: destination = operand one AND (NOT (operand two))
Flags: N,Z,(C)
#wrap on
#line
This instruction provides a useful way of clearing certain bits within a data word, while leaving others unchanged. Operand one is the data field to be modified, with the result being placed in the destination register.
#line
Operand two is a 32-bit word called the data mask. A set bit in the bit mask will force the corresponding bit in the data word to be reset when the instruction is executed. A zero bit in the mask will leave the corresponding bit in the data word in its original state.
#line
Examples:
#wrap off
#Indent 2
BIC	R0,R0,#%1111	Clear low 4 bits of R0
BIC	R1,R1,R2	Clear bits in R1 which were set in R2
BIC	R6,R6,R6	Clear bits which were set in R6 (R6 = 0)
#Indent
#wrap onDATAoTST: Test Bits
#background wimp 1
#wrap off
Syntax: TST \{\<suffix\>\} \<operand1\>, \<operand2\>
Operation: Reflect result of operand one AND operand two
Flags: N,Z,(C)
#wrap on
#line
This instruction performs the logical bitwise ANDing of operands one and two, but does not store the result anywhere - instead the status flags are altered to reflect the result.
#line
TST can be used to see if a particular bit in a data word is set or clear. The data word forms one operand. A bit mask, in which the appropriate bit is et, forms the other operand. After the TST operation the Z flag will be set if the bit is set in the data word, clear if it is not.
#line
Examples:
#wrap off
#Indent 2
TST	R1,#%1000	Test to see if bit 3 is set in R1
TST	R3,R4		Test if any bits set in both R3 and R4
#Indent
#wrap on
*Note*: This is another instruction where the S suffix is implied.DATATEQ: Test Equivalence
#background wimp 1
#wrap off
Syntax: TEQ \{\<suffix\>\} \<operand1\>, \<operand2\>
Operation: Reflect result of operand one EOR operand two
Flags: N,Z,(C)
#wrap on
#line
This instruction is very similar to <TST>. The only difference is that it performs a notional EOR operation between its operands, instead of an AND. The TEQ instruction can be used to see if the bits in two data words are the same or not.
#line
This comparison would normally be performed using <CMP>. However TEQ does not affect the carry flag, which may sometimes be useful.
#line
Examples:
#wrap off
#Indent 2
TEQ	R1,#5		Test to see if R1 contains 5
TEQ	R3,R4		Test to see if R3 = R4
#Indent
#wrap on
*Note*: This is another instruction where the S suffix is implied.DATAkMLA: Multiplication with Accumulate
#background wimp 1
#wrap off
Syntax: MLA \{\<suffix\>\} \<destination\>, \<operand1\>, \<operand2\>, \<sum\>
Operation: destination = (operand one * operand two) + sum
Flags: N,Z [V - unchanged; C - undefined]
#wrap on
#line
This instruction is similar to <MUL>, the difference being that the contents of the register given in the sum field are added into the result of the multiplication before storing it in the destination register. The restrictions which apply to <MUL> also apply to MLA.
#line
MLA is used to keep a running total of a series of multiplications. If the sum register is specified as being the same as the destination, then the result of each multiplication will be accumulated in the destination register.
#line
Examples:
#Indent 2
MLA	R0,R1,R2,R3	R0 = (R1 * R2) + R3
MLA	R0,R1,R2,R0	R0 = (R1 * R2) + R0
#IndentDATA�MUL: Multiplication
#background wimp 1
#wrap off
Syntax: MUL \{\<suffix\>\} \<destination\>, \<operand1\>, \<operand2\>
Operation: destination = operand one * operand two
Flags: N,Z [V - unchanged; C - undefined]
#wrap on
#line
This instruction performs 32-bit multiplication of the two operands, with the result being stored in the destination register.
#line
There are certain restrictions associated with the use of this instruction:
#wrap off
#Indent 2
- The 3 data fields specified must be simple registers
- The destination and operand1 must be different registers
- R15 may not be used as the destination register
#Indent
#wrap on
#line
Example:
#Indent 2
MUL	R0,R1,R3	R0 = R1 * R3
#IndentDATA�SWI: Software Interrupt
#background wimp 1
#wrap off
Syntax: SWI \<argument\> 
#wrap on
#line
When executed, this instruction causes the processor to break off from the current program. The ARM switches into supervisor mode and jumps to a pre-defined address in the OS. The argument field is then examined to determine which of the many OS facilities has been requested. When the appropriate routine has been completed, the ARM resumes the execution of the user program where it left off.
#line
Examples:
#Indent 2
SWI	"OS_Mouse"
SWI	"Wimp_CreateWindow"
#Indent
*Note*: The name of the routine must match up with that recognised by the assembler including the case of each character.DATAGB: Simple Branch
#background wimp 1
#wrap off
Syntax: B \<address\>
Operation: Jump to specified address
#wrap on
#line
This instruction is analogous to the BASIC GOTO statement - it makes the processor break off from its normal sequential execution of instructions and jump to a new instruction at a designated location.
#line
When used in conjunction with the normal condition codes, this instruction becomes the basis of conditional branching.
#line
Example:
#Indent 2
.loop
SUB	R0,R0,#1	R0 = R0 - 1
CMP	R0,#0		is R0 = 0?
BNE	loop		if not, go back to start of loop
#IndentDATA�BL: Branch with Link
#background wimp 1
#wrap off
Syntax: BL \<address\>
Operation: [MOV R14,PC] + Jump to specified address
#wrap on
#line
This instruction is analogous to the BASIC GOSUB statement - it makes the processor break off from its normal sequential execution of instructions and jump to a new instruction at a designated location. By moving the contents of R14 back into PC, we can return to the original Branch instruction.
#line
When used in conjunction with the normal condition codes, this instruction becomes the basis of conditional branching.
#line
Example:
#Indent 2
.loop
SUB	R0,R0,#1	R0 = R0 - 1
CMP	R0,#0		is R0 = 0?
BNE	loop		if not, go back to start of loop
BL	subroutine	otherwise, go to subroutine
...
.subroutine
MOV PC,R14		return to main code
#Indent
#line; wrap nojoin
*Note*: It is important that the contents of R14 are stored elsewhere prior to using this instruction. This can be done using a <stack=>stacks>.
The command 'MOV PC,R14' will mean that the original status flag settings will not be restored once the subroutine has returned. Should the user want the flags to be unaffected by the subroutine, the command should be modified to 'MOVS PC,R14'.
#wrap onDATA�LDR: Load to Register
#background wimp 1
#wrap off
Operation: Data transfer from memory to the registers
#wrap on
#line
This instruction is used to transfer data from memory into the registers. A system of indirect addressing is used to specify the source location address - the address to be looked up is held in a register.
There are two forms of indirect addressing: <Pre-indexed=>Pre> and <Post-indexed=>Post>. In addition to these two forms, a <PC relative=>PC_rel> address can also be specified.DATASTR: Store from Register
#background wimp 1
#wrap off
Operation: Data transfer from the registers to memory
#wrap on
#line
This instruction is used to transfer data from the registers into memory. A system of indirect addressing is used to specify the destination location address - the address to be looked up is held in a register.
There are two forms of indirect addressing: <Pre-indexed=>Pre> and <Post-indexed=>Post>. In addition to these two forms, a <PC relative=>PC_rel> address can also be specified.DATA6Byte addressing
#background wimp 1
By default, <LDR> and <STR> access complete words of memory (four bytes). However, they can be made to access single bytes using the 'B' suffix.
#line
Examples:
#wrap off
#indent 2
LDRB	R0,[R2,R4]
STRB	R0,[R5,#4]
LDRB	R0,[R6,R5,LSR#6]!
LDRNEB	R0,[R1],R3
LDRB	R0,tableDATA�PC relative addressing
#background wimp 1
#wrap off
Syntax: LDR (or STR) \<destination\>,address
#wrap nojoin
#line
PC relative addressing is a pseudo-addressing mode as it is not a distinct addressing mode supported by the ARM. Instead, such instructions are converted into an appropriate pre-indexed instruction by the assembler.
The address is simply an absolute number, or an assembler label.
#line
Examples:
#wrap off
#indent 2
LDR R0,&1000	Load word of memory from location &1000 into R0
STR R0,table	Store R0 to word of memory specified by 'table'
#indent
#wrap on
#line
It is important to remember that the range of the offset, as in <pre-indexed addressing=>Pre>, is between -4096 and 4096.DATAcPost-indexed addressing
#background wimp 1
#wrap off
Syntax: LDR (or STR) \<destination\>, [\<base\>],\<offset\>
#wrap on
#line
This form of addressing is very similar to <pre-indexed addressing=>Pre>. In this case, however, the offset field is *not* optional.
#line
Examples:
#wrap off
#indent 2
LDR R1,[R0],R7		Load R1 from address R0	: R0=R0+R7
STR R6,[R7],#4		Store R6 at address R7	: R7=R7+4
LDR R8,[R2],R5,LSL#4	Load R8 from address R2	: R2=R2+R5*16
STR R0,[R0],#20		Store R0 at address R0	: R0=R0+20
#indent
#wrap on
#line
When post-indexed addressing is used, the contents of the base register alone are taken as the address of the memory word to be accessed. Only after this word has been accessed are the contents of the offset field added to the base register. Obviously, this implies that write back always occurs, so we do not need to specify it.DATA!Pre-indexed addressing
#background wimp 1
#wrap off
Syntax: LDR (or STR) \<destination\>, [\<base\>\{,\<offset\>\}]
#wrap on
#line
The destination field is the register into which the data will be transferred. The contents of the base and offset fields together specify the memory word to be accessed. The offset field is optional - if present, it will be added to the base field to give the required address. The offset field is specified in the same way as operand two in the data processing instructions.
#line
Examples:
#wrap off
#indent 2
LDR R0,[R1]		Load R0 from address R1
STR R0,[R1,R2]		Store R0 at address R1 + R2
LDR R0,[R1,#-4]		Load R0 from address R1 - 4
STR R0,[R1,R2,LSL#2]	Store R0 at address R1 + R2*4
#indent
#line
A further level of complexity is that of <write back=>wb>
DATARWrite Back
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#wrap on
In calculating which word of memory is to be accessed, the ARM adds together the contents of the base and offset registers. It is sometimes useful to retain this newly calculated address for future use. In pre-indexed addressing, this is done by using the ARM's 'write back' facility.
#line
Write back is specified with the '!' suffix.
#wrap off
Examples:
#indent 2
LDR R0,[R1,R2]!		Load R0 from address R1+R2	: R1=R1+R2
STR R3,[R5,#10]!	Store R3 at address R5+R10	: R5=R5+10
LDR R7,[R3,R8,LSL#2]!	Load R7 from address R3+R8*4	: R3=R3+R8*4
#indent
#wrap nojoin
#line
When the ARM executes the instruction, it will perform the usual addition of the base and offset fields. It will then access the data at the newly calculated address. Finally, as write back is selected, it will store the newly calculated address back into the base register.
Write back is particularly useful when accessing a sequence of memory locations, e.g., to access consecutive memory words we can use 'LDR R0,[base,#4]!'. Write back hence allows the easy creation and access of arrays.DATA�LDM: Load Multiple Registers
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#wrap off
Syntax: LDM \<options\> \<base\> \{!\}, \<register\_list\>
Operation: Multiple transfer of data from the registers to memory
#wrap nojoin
#line
The register_list is the series of register names, separated by commas, the contents of which we want to load from memory. The order of the registers in the list is of no significance, and any number of registers can be loaded. The assembler will allow a range of registers to be specified by using a '-' character.
The base field must be given as a simple register. The contents of this are taken to be the start address in memory from which the registers are to be loaded.
The <options=>M_opts> field is a two-character code which defines how the instruction should be executed.
#line
As the ARM executes the instruction, it will load consecutive memory words into each of the registers named in register_list. A copy of the address in the base register is used and modified by the ARM as each register is stored. The actual contents of the base are not changed, unless we request this using the <write back=>M_wb> option.
#line
Taken at its simplest level, LDM can be used to restore the contents of a register group previously stored with an <STM> instruction, containing the same memory address and register_list. However, a major use of <STM> and LDM is in the creation and access of <stacks>.DATA�STM: Store Multiple Registers
#background wimp 1
#wrap off
Syntax: STM \<options\> \<base\> \{!\}, \<register\_list\>
Operation: Multiple transfer of data from the registers to memory
#wrap nojoin
#line
The register_list is the series of register names, separated by commas, the contents of which we want to store in memory. The order of the registers in the list is of no significance, and any number of registers can be stored. The assembler will allow a range of registers to be specified by using a '-' character.
The base field must be given as a simple register. The contents of this are taken to be the start address in memory from which the registers are to be saved.
The <options=>M_opts> field is a two-character code which defines how the instruction should be executed.
#line
As the ARM executes the instruction, it will store the contents of each of the registers named in register_list in consecutive memory words. A copy of the address in the base register is used and modified by the ARM as each register is stored. The actual contents of the base are not changed, unless we request this using the <write back=>M_wb> option.
#line
Taken at its simplest level, STM can be used to preserve the contents of a register group in an arbitrary block of memory. The original contents can then be restored at a later time using <LDM> with the same memory address and register_list. However, a major use of STM and <LDM> is in the creation and access of <stacks>.DATA�STM & LDM options
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#wrap on
*Direction of Storage*
The storage / loading direction used by the instruction is controlled by the first character in the option field. This may be either of the following:
#wrap off
#indent 2
I	Increment address after storing / loading each register
D	Decrement address after storing / loading each register
#indent
#wrap on
If an incrementing address is specified, then registers will be stored in / loaded from locations: 'base', 'base+4', 'base+8', etc. The reverse will occur with a decrementing address.
#line
*Pre or Post Address Modification*
The second letter in the option field specifies whether the address is to be modified before or after each register is stored / loaded. The following options can be used:
#wrap off
#indent 2
A	Modify address after storing / loading each register
B	Modify address before storing / loading each register
#indent
#wrap nojoin
If the address is modified after storing / loading each register, then the first register will be stored / loaded at the address in base, and the second at (base+4) or (base-4), depending on the increment / decrement option.
If the address is modified before storing / loading each register, then the first address will be stored / loaded at the address in (base+4) or (base-4), again depending on the increment / decrement option. The second register will be stored / loaded at (base+8) or (base-8), etc.DATA�Write back with STM & LDM
#background wimp 1
As the ARM stores or loads registers, it modifies the address being used. This ensures that the next register processed is stored or loaded in a consecutive word of memory, so that one word is not used twice. If we specify that we want write back, then the final address, obtained after storing or loading all the registers in the list, will be written back into the base register.
#line
Write back is selected, as with <STR> and <LDR>, by including a '!' character. Thus, the following instructions all have write back selected:
#wrap off
#indent 2
STMIA	R0!,\{R1,R2\}
STMDA	(base)!,\{R4,R5-R9\}
LDMIB	R6!,\{R12,R11,R10\}
#indent
#wrap on
*NB*: Note the use of round brackets when the variable 'base' is used to refer to a register. This prevents the assembler interpreting the '!' as an indirection operator and causing an error.
#line
After each instruction, the ARM performs one of the following depending on the direction of storage used:
#wrap off
#indent 2
base = base + 4*n	(increment)
base = base - 4*n	(decrement)
#indent
#wrap on
Where 'n' is the number of registers stored by the instruction. Write back is provided so as to provide support the creation of <stacks> using the LDM / STM instructions.
DATA�Stacks
#background wimp 1
A stack is a data structure used to store the contents of registers for later use. A series of contiguous memory locations are set aside to hold the data. A pointer is used to record where the top of the stack is. When an item is added to the stack, we store it in the memory word pointed to by the stack pointer. We then increment the pointer to point to the next word.
When we remove an item from the stack, we first decrement the stack pointer and then access the memory word which it points to. The stack is therefore a 'last in, first out' (LIFO) structure.
#line
#wrap off
There are four possible stack structures, which are made of combinations of two variants.
#wrap nojoin
The first of these variants determines which direction the stack grows in. We can create stacks that grow upwards in memory as extra items are pushed on, and contract downwards as items are pulled off (ascending stack), or the opposite, where the stack grows downwards in memory as items are added, and contracts back up again as they are pulled off (descending stack).
When a stack is implemented, you must decide exactly what the stack pointer should point to. It could point to the top entry on the stack, i.e., the one most recently pushed on the stack ('full'), or alernatively, it may point to the next available space in the stack's memory area, i.e., the address a which a new item would be stored if it were pushed onto the stack ('empty').
Hence the four stack structures are:
#wrap off
#indent 2
(1)	Full, ascending stack
(2)	Full, descending stack
(3)	Empty, ascending stack	    *Most useful*
(4)	Empty, descending stack
#indent
#wrap nojoin
#line
The <LDM> and <STM> instructions provide the facilities to implement stacks in machine code. The elements pushed to, and pulled from, the stack are the register contents specified in the instruction's register list.
The stack pointer is implemented using the instruction's base register. This always points to the address in memory where the instruction will store or load data. R13 is used most often for this purpose although any register could be used.
#line
#align centre
<Implementing stacks=>stacks2>DATAxImplementing stacks
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#wrap nojoin
Initially, the stack pointer will be set to contain the base address of the stack's memory area. Write back can then be used with the <LDM> and <STM> instructions to make the ARM automaticallt update the stack pointer each time registers are pushed to the stack or pulled off it.
For an empty ascending stack, the following instructions are used:
#indent 2
Push registers
#indent 4
STMIA R13!,\{register_list\}
#indent
Pull registers
#indent 4
LDMDB R13!,\{register_list\}
#indent
#indent
*NB*: The use of write back is vital - without it the stack pointer will never be updated, and the stack will be corrupted.
#line
The options for the STM instruction are always reversed in the case of the LDM instruction. It can be confusing to have to translate the stack type used into the appropriate options, so the assembler provides an easier way.
We can simply specify the type of stack being used, which will be the same for both instructions:
#indent 2
FA	Full, ascending stack
FD	Full, descending stack
EA	Empty, ascending stack
ED	Empty, descending stack
#indent
The assembler will then choose appropriate options for the instruction.
The empty ascending stack could thus be implemented as follows:
#indent 2
Push registers
#indent 4
STMEA R13!,\{register_list\}
#indent
Pull registers
#indent 4
LDMEA R13!,\{register_list\}
#indent
#indentDATA�EQU: Storing Data
#background wimp 1
#wrap on
This pseudo opcode allows us to reserve given amounts of memory for storing text strings, data tables, variables, etc. It also allows us to define the contents of the memory reserved.
#line
The EQU opcodes provided are described below:
#wrap off
#tab
#indent 9
*Name*	*Function*
EQUB	Reserve one byte
EQUW	Reserve two bytes (one 'word')
EQUD	Reserve four bytes (double 'word')
EQUS	Reserve string (zero to 255 characters)
#indent
#wrap nojoin
When one of these directives is assembled, the argument following it is evaluated and the result is stored in memory. The value of <P%> is then incremented by the appropriate amount.
All strings stored with EQUS should terminate with a zero byte.DATAL%: Upper Limit for Range Check
#background wimp 1
#wrap on
The contents of this integer variable tell the assembler where the upper memory limit for the object code is. If range checking is specified in the <OPT> code, an error message will be sent if this limit is reached.DATAOPT
#background wimp 1
#wrap on
This pseudo opcode does not produce any machine code, but directs the assembler to perform a number of functions, which are described in the following table:
#wrap off
#align centre
#indent 17
#tab
	*Range*	*Offset*	*Errors*	*Listing*
	*Check*	*Assembly*	*Reported*	*Produced*
OPT 0	No	No	No	No
OPT 1	No	No	No	Yes
OPT 2	No	No	Yes	No
OPT 3	No	No	Yes	Yes
OPT 4	No	Yes	No	No
OPT 5	No	Yes	No	Yes
OPT 6	No	Yes	Yes	No
OPT 7	No	Yes	Yes	Yes
OPT 8	Yes	No	No	No
OPT 9	Yes	No	No	Yes
OPT 10	Yes	No	Yes	No
OPT 11	Yes	No	Yes	Yes
OPT 12	Yes	Yes	No	No
OPT 13	Yes	Yes	No	Yes
OPT 14	Yes	Yes	Yes	No
OPT 15	Yes	Yes	Yes	Yes
#tab
#indent
#align centre
(The default value is 3)
#align
#line
#wrap on
When a program written in assembly language is assembled, it should be done twice - once with OPT 0 (or OPT 8), then again with OPT 3 (or OPT 11). This allows the assembler to 'see' all the labels before it actually assembles the program. The two-pass system can easily be implemented with a FOR...NEXT loop.
#line
Range checking allows the user to inform the assembler of the upper boundary of the memory reserved for its object code. It will then issue a warning and abort if this limit is reached. The integer variable <L%> should contain the upper memory limit.DATAWP%: Assembler Location Counter
#background wimp 1
#wrap on
The contents of this integer variable tell the assembler the address at which we want the machine code program to start. At any given time, P% will always hold the address in memory where the next instruction will be written to.
#line
#align centre
<Reserving memory=>Reserve>DATA0Reserving memory for assembly programs
#background wimp 1
#wrap on
The BASIC assembler makes no checks on the value of <P%> to determine whether or not the memory which it points to is 'safe' to use. The simplest way to reserve a safe area of memory is to use a special form of the DIM statement:
#wrap off
#indent 2
DIM \<variable\> \<number\>
#indent
#wrap nojoin
'Variable' is any numeric variable, and 'number' is the number of bytes of memory to be reserved. For example, 'DIM code 1024' will reserve 1024 bytes of memory, and will set the variable 'code' to point to the first of these bytes. The address returned is also guaranteed to be word-aligned.
We can now tell the assembler to use the reserved area of memory, for storing machine code in, by the simple instruction:
#indent 2
P% = code
#indentDATA�ADR
#background wimp 1
#wrap on
It is often very useful to be able to get the actual address associated with a label into one of the processor registers. For example, the label could mark the beginning of a data table in a program. For this we would need to have this address in a register to access entries in the table. ADR can be used for this purpose.
#line
#wrap off
Syntax: ADR \<register\>, \<label\>
#wrap on
'Register' is the name of the register which is to contain the address of the label.DATA_ALIGN
#background wimp 1
#wrap on
This pseudo opcode does not produce any machine code, but directs the assembler to check the value of <P%> to check whether the address it contains is word-aligned. If not, P% is rounded up to the next word boundary.
#line
P% is often not word-aligned after <EQUB=>EQU>, <EQUW=>EQU> or <EQUS=>EQU> directives.DATAPassing data from BASIC to the assembler
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#wrap nojoin
It is often necessary to pass data from a BASIC program to amachine code routine. The <CALL> statement has some advanced extensions for this purpose - however, this is complicated. Up to eight 32-bit integers can be passed to the assembler very easily, simply by placing them into the integer variables A% to H%.
Just before transferring control to a machine code routine, BASIC copies the values of the integer variables into the processor registers R0 to R7.DATA�Returning data to BASIC
#background wimp 1
#wrap nojoin
If we want to pass an integer variable back from a machine code routine to BASIC, then we can use the USR statement:
#wrap off
#indent 2
\<variable\> = USR( \<address\> )
#indent
#line
#wrap on
This is similar to <CALL> because it causes BASIC to execute a machine code routine at a specified address. However, when BASIC is returned to, USR returns the contents of R0 into 'variable'.DATA�Pipeline suspend
#background wimp 1
#wrap on
The 'P' suffix disables pipelining to allow writing to R15. The result of the operand (usually TEQ) is written back *directly* to the status bits (26-31) of R15.FREE@���� The Link Register
#background wimp 1
#wrap nojoin
TFREE0�� Program Counter & Status Register
#background wimp 1
#wrap on
Register R15 is a special purpose register dedicated to maintaining the ARM's program counter, status flags and mode flags.

#Fcode; wrap off
Bit: 31 30 29 28 27 26 25		  2  1  0
R15:  N  Z  C  V  I  F ...Program Counter... S1 S0FREE � Program Counter & Status Register
#background wimp 1
#wrap on
Register R15 is a special purpose register dedicated to maintaining the ARM's program counter, status flags and mode flags.
Bit: 31 30 29 28 27 26 25		  2  1  0
R15:  N  Z  C  V  I  F ...Program Counter... S1 S0DATAXCALL
#background wimp 1
#wrap off
Syntax: CALL \<address\> \{,\<parameters\>\}
Operation: Initiates machine code routine at given address
#wrap on
#line
The optional parameters are a list a comma-separated BASIC variables, the values of which are to be made available to the machine code routine. So, in addition to setting up registers R0 to R8 from the integer variables, CALL also sets up the following two registers:
#wrap off
#indent 2
R9:	Pointer to parameters descriptor block
R10:	Number of parameters passed using CALL
#indent
#wrap nojoin
Register R9 points to the memory block where a parameter list has been created. This list has a two-word entry in it for each variable in the parameter list. An important point to note is that the entries in the parameter block are set up in reverse order.
The first word of each entry is a pointer to the address where the variable itself is stored. The second word contains a number which represents the type of variable passed. The table below lists the different type numbers:
#wrap off
#indent 12
#tab
*Type*	*Object address*	*Examples of possible*
*number*	*points to*	*BASIC variables*
0	Single byte number	?var
4	Four-byte integer	!var, var%, var%(n)
5	Real number (5 bytes)	var, var(n)
128	String information block	var$, var$(n)
129	Terminated character string	$var
256+4	Integer array block	var%()
256+5	Real array block	var()
256+128	String array block	var$()
#tab
#indent
#wrap nojoin
*NB*: The values of variables are not guaranteed to be stored at word-aligned addresses.
In the case of parameter types 4, 5, and 129 their address points to the variable value. In other cases the address points to another information block about the corresponding variable.
For BASIC string variables (type 128) the address in the parameter block points to a string information block. This block is guaranteed to exist at a word-aligned address and has the following format:
#indent 2
Bytes 0-3	Pointer to the characters contained in the string
Byte 4		Current number of characters in the string
#indent
Variables of type 256+ refer to arrays and require a more complicated system.DATAzCredits and Copyright
#background wimp 1
#wrap nojoin
This manual is an updated version of the 'Assembly' manual, previously supplied with !StrongHelp, by Guttorm Vik. The information was obtained from 'Archimedes Assembly Language' (2nd ed.) by Mike Ginns.
#line
#align centre
*Updated by Jasper the Apricot*
m.d.field@warwick.ac.uk
http://www.csv.warwick.ac.uk/~lsuqf
DATAqR14: The Link Register
#background wimp 1
#wrap nojoin
The link register is used to provide a degree of support for implementing subroutines in machine code. R14 is used to store the address the program returns to once a subroutine has finished.

R14 is used each time the <BL> instruction is carried out. At other times it is unused and is free for normal use.DATA>R15: Program Counter & Status Register
#background wimp 1
#wrap on
Register R15 is a special purpose register dedicated to maintaining the ARM's program counter, status flags and mode flags.

#Fcode; wrap off
Bit: 31 30 29 28 27 26         .....          1  0
R15:  N  Z  C  V  I  F ...Program Counter... S1 S0
00000000  48 45 4c 50 28 00 00 00  c9 00 00 00 60 9c 00 00  |HELP(.......`...|
00000010  2c 00 00 00 00 fd ff ff  00 00 00 00 44 06 00 00  |,...........D...|
00000020  00 01 00 00 00 00 00 00  24 00 00 00 44 49 52 24  |........$...DIR$|
00000030  4c 06 00 00 4c 06 00 00  78 06 00 00 46 ff ff ff  |L...L...x...F...|
00000040  70 2d 9f d0 21 04 00 00  13 00 00 00 00 00 00 00  |p-..!...........|
00000050  21 52 6f 6f 74 00 00 00  9c 0a 00 00 46 ff ff ff  |!Root.......F...|
00000060  33 da 2c 82 d6 03 00 00  13 00 00 00 00 00 00 00  |3.,.............|
00000070  63 6f 6e 64 00 00 00 00  74 0e 00 00 46 ff ff ff  |cond....t...F...|
00000080  3d ec a9 79 e1 00 00 00  13 00 00 00 00 00 00 00  |=..y............|
00000090  4f 70 32 00 58 0f 00 00  46 ff ff ff ba c1 a9 79  |Op2.X...F......y|
000000a0  8a 00 00 00 13 00 00 00  00 00 00 00 52 64 00 00  |............Rd..|
000000b0  e4 0f 00 00 46 ff ff ff  5b c5 a9 79 9b 00 00 00  |....F...[..y....|
000000c0  13 00 00 00 00 00 00 00  52 6e 00 00 80 10 00 00  |........Rn......|
000000d0  46 ff ff ff 27 03 aa 79  db 00 00 00 13 00 00 00  |F...'..y........|
000000e0  00 00 00 00 53 00 00 00  5c 11 00 00 46 ff ff ff  |....S...\...F...|
000000f0  0f cd a9 79 c2 01 00 00  13 00 00 00 00 00 00 00  |...y............|
00000100  53 68 69 66 74 00 00 00  20 13 00 00 46 ff ff ff  |Shift... ...F...|
00000110  21 fe 1a 76 59 03 00 00  13 00 00 00 00 00 00 00  |!..vY...........|
00000120  41 44 43 00 7c 16 00 00  46 ff ff ff df 01 1b 76  |ADC.|...F......v|
00000130  0e 02 00 00 13 00 00 00  00 00 00 00 41 44 44 00  |............ADD.|
00000140  8c 18 00 00 46 ff ff ff  c4 21 1b 76 10 03 00 00  |....F....!.v....|
00000150  13 00 00 00 00 00 00 00  52 53 42 00 9c 1b 00 00  |........RSB.....|
00000160  46 ff ff ff af 6c 19 76  e7 02 00 00 13 00 00 00  |F....l.v........|
00000170  00 00 00 00 53 42 43 00  84 1e 00 00 46 ff ff ff  |....SBC.....F...|
00000180  9a 28 1b 76 fc 01 00 00  13 00 00 00 00 00 00 00  |.(.v............|
00000190  53 55 42 00 80 20 00 00  46 ff ff ff a0 24 1b 76  |SUB.. ..F....$.v|
000001a0  bd 02 00 00 13 00 00 00  00 00 00 00 52 53 43 00  |............RSC.|
000001b0  40 23 00 00 46 ff ff ff  bd 17 1b 76 4e 02 00 00  |@#..F......vN...|
000001c0  13 00 00 00 00 00 00 00  4d 4f 56 00 90 25 00 00  |........MOV..%..|
000001d0  46 ff ff ff ba 1a 1b 76  a6 02 00 00 13 00 00 00  |F......v........|
000001e0  00 00 00 00 4d 56 4e 00  38 28 00 00 46 ff ff ff  |....MVN.8(..F...|
000001f0  c6 49 19 76 b8 03 00 00  13 00 00 00 00 00 00 00  |.I.v............|
00000200  43 4d 50 00 f0 2b 00 00  46 ff ff ff cc 0e 1b 76  |CMP..+..F......v|
00000210  18 03 00 00 13 00 00 00  00 00 00 00 43 4d 4e 00  |............CMN.|
00000220  08 2f 00 00 46 ff ff ff  40 05 1b 76 17 02 00 00  |./..F...@..v....|
00000230  13 00 00 00 00 00 00 00  41 4e 44 00 20 31 00 00  |........AND. 1..|
00000240  46 ff ff ff 80 14 1b 76  44 02 00 00 13 00 00 00  |F......vD.......|
00000250  00 00 00 00 45 4f 52 00  64 33 00 00 46 ff ff ff  |....EOR.d3..F...|
00000260  1f 1e 1b 76 72 02 00 00  13 00 00 00 00 00 00 00  |...vr...........|
00000270  4f 52 52 00 d8 35 00 00  46 ff ff ff 63 0b 1b 76  |ORR..5..F...c..v|
00000280  8a 03 00 00 13 00 00 00  00 00 00 00 42 49 43 00  |............BIC.|
00000290  64 39 00 00 46 ff ff ff  d2 f9 1a 76 6f 03 00 00  |d9..F......vo...|
000002a0  13 00 00 00 00 00 00 00  54 53 54 00 d4 3c 00 00  |........TST..<..|
000002b0  46 ff ff ff d4 c3 1b 76  02 03 00 00 13 00 00 00  |F......v........|
000002c0  00 00 00 00 54 45 51 00  d8 3f 00 00 46 ff ff ff  |....TEQ..?..F...|
000002d0  85 e0 1c 76 6b 03 00 00  13 00 00 00 00 00 00 00  |...vk...........|
000002e0  4d 4c 41 00 44 43 00 00  46 ff ff ff df 04 1d 76  |MLA.DC..F......v|
000002f0  c0 02 00 00 13 00 00 00  00 00 00 00 4d 55 4c 00  |............MUL.|
00000300  04 46 00 00 46 ff ff ff  be b9 1d 76 b3 02 00 00  |.F..F......v....|
00000310  13 00 00 00 00 00 00 00  53 57 49 00 b8 48 00 00  |........SWI..H..|
00000320  46 ff ff ff 51 59 93 76  47 02 00 00 13 00 00 00  |F...QY.vG.......|
00000330  00 00 00 00 42 00 00 00  00 4b 00 00 46 ff ff ff  |....B....K..F...|
00000340  b8 87 c2 79 b6 04 00 00  13 00 00 00 00 00 00 00  |...y............|
00000350  42 4c 00 00 b8 4f 00 00  46 ff ff ff aa 8c b0 79  |BL...O..F......y|
00000360  fd 01 00 00 13 00 00 00  00 00 00 00 4c 44 52 00  |............LDR.|
00000370  b8 51 00 00 46 ff ff ff  1d 9a b0 79 05 02 00 00  |.Q..F......y....|
00000380  13 00 00 00 00 00 00 00  53 54 52 00 c0 53 00 00  |........STR..S..|
00000390  46 ff ff ff 40 56 b0 79  36 01 00 00 13 00 00 00  |F...@V.y6.......|
000003a0  00 00 00 00 42 79 74 65  00 00 00 00 f8 54 00 00  |....Byte.....T..|
000003b0  46 ff ff ff 30 3f b1 79  c3 02 00 00 13 00 00 00  |F...0?.y........|
000003c0  00 00 00 00 50 43 5f 72  65 6c 00 00 bc 57 00 00  |....PC_rel...W..|
000003d0  46 ff ff ff 64 bf af 79  63 03 00 00 13 00 00 00  |F...d..yc.......|
000003e0  00 00 00 00 50 6f 73 74  00 00 00 00 20 5b 00 00  |....Post.... [..|
000003f0  46 ff ff ff f6 62 ab 79  21 03 00 00 13 00 00 00  |F....b.y!.......|
00000400  00 00 00 00 50 72 65 00  44 5e 00 00 46 ff ff ff  |....Pre.D^..F...|
00000410  09 1c af 79 52 04 00 00  13 00 00 00 00 00 00 00  |...yR...........|
00000420  77 62 00 00 98 62 00 00  46 ff ff ff 34 48 bc 79  |wb...b..F...4H.y|
00000430  81 05 00 00 13 00 00 00  00 00 00 00 4c 44 4d 00  |............LDM.|
00000440  1c 68 00 00 46 ff ff ff  4f 43 bc 79 c5 05 00 00  |.h..F...OC.y....|
00000450  13 00 00 00 00 00 00 00  53 54 4d 00 e4 6d 00 00  |........STM..m..|
00000460  46 ff ff ff 58 2f bc 79  9a 05 00 00 13 00 00 00  |F...X/.y........|
00000470  00 00 00 00 4d 5f 6f 70  74 73 00 00 80 73 00 00  |....M_opts...s..|
00000480  46 ff ff ff c9 a3 bd 79  f1 04 00 00 13 00 00 00  |F......y........|
00000490  00 00 00 00 4d 5f 77 62  00 00 00 00 74 78 00 00  |....M_wb....tx..|
000004a0  46 ff ff ff 88 1c c0 79  86 08 00 00 13 00 00 00  |F......y........|
000004b0  00 00 00 00 73 74 61 63  6b 73 00 00 fc 80 00 00  |....stacks......|
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00001fa0  74 73 20 66 69 72 73 74  20 6f 70 65 72 61 6e 64  |ts first operand|
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00002000  55 42 09 52 31 30 2c 52  32 2c 52 34 09 52 31 30  |UB.R10,R2,R4.R10|
00002010  20 3d 20 52 32 20 2d 20  52 34 0a 53 55 42 4d 49  | = R2 - R4.SUBMI|
00002020  09 52 31 2c 52 33 2c 23  31 30 32 34 09 49 66 20  |.R1,R3,#1024.If |
00002030  6e 65 67 20 66 6c 61 67  20 73 65 74 20 52 31 20  |neg flag set R1 |
00002040  3d 20 52 33 20 2d 20 31  30 32 34 0a 53 55 42 09  |= R3 - 1024.SUB.|
00002050  52 30 2c 52 30 2c 52 30  2c 4c 53 4c 23 31 09 52  |R0,R0,R0,LSL#1.R|
00002060  30 20 3d 20 52 30 20 2d  20 32 2a 52 30 20 28 52  |0 = R0 - 2*R0 (R|
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000020f0  2c 20 5c 3c 6f 70 65 72  61 6e 64 31 5c 3e 2c 20  |, \<operand1\>, |
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00002110  72 61 74 69 6f 6e 3a 20  64 65 73 74 69 6e 61 74  |ration: destinat|
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00002150  61 67 73 3a 20 4e 2c 5a  2c 43 2c 56 0a 23 77 72  |ags: N,Z,C,V.#wr|
00002160  61 70 20 6f 6e 0a 23 6c  69 6e 65 0a 54 68 69 73  |ap on.#line.This|
00002170  20 6f 70 65 72 61 74 69  6f 6e 20 70 65 72 66 6f  | operation perfo|
00002180  72 6d 73 20 61 20 72 65  76 65 72 73 65 20 73 75  |rms a reverse su|
00002190  62 74 72 61 63 74 20 6f  70 65 72 61 74 69 6f 6e  |btract operation|
000021a0  20 77 68 69 6c 65 20 74  61 6b 69 6e 67 20 61 63  | while taking ac|
000021b0  63 6f 75 6e 74 20 6f 66  20 61 20 70 72 65 76 69  |count of a previ|
000021c0  6f 75 73 20 62 6f 72 72  6f 77 20 69 6e 20 74 68  |ous borrow in th|
000021d0  65 20 63 61 72 72 79 20  66 6c 61 67 2e 0a 23 6c  |e carry flag..#l|
000021e0  69 6e 65 0a 54 68 69 73  20 6f 70 65 72 61 6e 64  |ine.This operand|
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00002200  20 73 75 62 74 72 61 63  74 69 6f 6e 20 74 6f 20  | subtraction to |
00002210  62 65 20 70 65 72 66 6f  72 6d 65 64 20 6f 6e 20  |be performed on |
00002220  6d 75 6c 74 69 2d 77 6f  72 64 20 6f 70 65 72 61  |multi-word opera|
00002230  6e 64 73 2e 20 49 74 20  63 6f 72 72 65 73 70 6f  |nds. It correspo|
00002240  6e 64 73 20 74 6f 20 74  68 65 20 3c 53 42 43 3e  |nds to the <SBC>|
00002250  20 69 6e 73 74 72 75 63  74 69 6f 6e 20 69 6e 20  | instruction in |
00002260  74 68 65 20 73 61 6d 65  20 77 61 79 20 74 68 61  |the same way tha|
00002270  74 20 3c 52 53 42 3e 20  63 6f 72 72 65 73 70 6f  |t <RSB> correspo|
00002280  6e 64 73 20 74 6f 20 3c  53 55 42 3e 2e 0a 23 6c  |nds to <SUB>..#l|
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000022a0  72 61 70 20 6f 66 66 0a  23 49 6e 64 65 6e 74 20  |rap off.#Indent |
000022b0  32 0a 52 53 42 53 09 72  65 73 75 6c 74 5f 6c 6f  |2.RSBS.result_lo|
000022c0  77 2c 20 6c 6f 77 31 2c  20 6c 6f 77 32 09 09 52  |w, low1, low2..R|
000022d0  65 76 65 72 73 65 20 73  75 62 74 72 61 63 74 20  |everse subtract |
000022e0  6c 6f 77 20 77 6f 72 64  73 0a 52 53 43 53 09 72  |low words.RSCS.r|
000022f0  65 73 75 6c 74 5f 68 69  67 68 2c 20 68 69 67 68  |esult_high, high|
00002300  31 2c 20 68 69 67 68 32  09 52 65 76 65 72 73 65  |1, high2.Reverse|
00002310  20 73 75 62 74 72 61 63  74 20 68 69 67 68 20 77  | subtract high w|
00002320  6f 72 64 73 20 2b 20 63  61 72 72 79 0a 23 49 6e  |ords + carry.#In|
00002330  64 65 6e 74 0a 23 77 72  61 70 20 6f 6e 00 00 00  |dent.#wrap on...|
00002340  44 41 54 41 4e 02 00 00  4d 4f 56 3a 20 4d 6f 76  |DATAN...MOV: Mov|
00002350  65 20 44 61 74 61 0a 23  62 61 63 6b 67 72 6f 75  |e Data.#backgrou|
00002360  6e 64 20 77 69 6d 70 20  31 0a 23 77 72 61 70 20  |nd wimp 1.#wrap |
00002370  6f 66 66 0a 53 79 6e 74  61 78 3a 20 4d 4f 56 20  |off.Syntax: MOV |
00002380  5c 7b 5c 3c 73 75 66 66  69 78 5c 3e 5c 7d 20 5c  |\{\<suffix\>\} \|
00002390  3c 64 65 73 74 69 6e 61  74 69 6f 6e 5c 3e 2c 20  |<destination\>, |
000023a0  5c 3c 6f 70 65 72 61 6e  64 32 5c 3e 0a 4f 70 65  |\<operand2\>.Ope|
000023b0  72 61 74 69 6f 6e 3a 20  64 65 73 74 69 6e 61 74  |ration: destinat|
000023c0  69 6f 6e 20 3d 20 6f 70  65 72 61 6e 64 20 74 77  |ion = operand tw|
000023d0  6f 0a 46 6c 61 67 73 3a  20 4e 2c 5a 2c 28 43 29  |o.Flags: N,Z,(C)|
000023e0  0a 23 77 72 61 70 20 6f  6e 0a 23 6c 69 6e 65 0a  |.#wrap on.#line.|
000023f0  54 68 69 73 20 69 6e 73  74 72 75 63 74 69 6f 6e  |This instruction|
00002400  20 6d 6f 76 65 73 20 64  61 74 61 20 69 6e 74 6f  | moves data into|
00002410  20 74 68 65 20 64 65 73  74 69 6e 61 74 69 6f 6e  | the destination|
00002420  20 72 65 67 69 73 74 65  72 2e 20 4f 70 65 72 61  | register. Opera|
00002430  6e 64 20 74 77 6f 2c 20  61 73 20 65 78 70 65 63  |nd two, as expec|
00002440  74 65 64 2c 20 63 61 6e  20 62 65 20 73 70 65 63  |ted, can be spec|
00002450  69 66 69 65 64 20 61 73  20 61 20 72 65 67 69 73  |ified as a regis|
00002460  74 65 72 2c 20 61 6e 20  69 6d 6d 65 64 69 61 74  |ter, an immediat|
00002470  65 20 6f 70 65 72 61 6e  64 20 6f 72 20 61 73 20  |e operand or as |
00002480  61 20 73 68 69 66 74 65  64 20 72 65 67 69 73 74  |a shifted regist|
00002490  65 72 2e 0a 23 6c 69 6e  65 0a 45 78 61 6d 70 6c  |er..#line.Exampl|
000024a0  65 73 3a 0a 23 77 72 61  70 20 6f 66 66 0a 23 49  |es:.#wrap off.#I|
000024b0  6e 64 65 6e 74 20 32 0a  4d 4f 56 09 52 31 32 2c  |ndent 2.MOV.R12,|
000024c0  52 30 09 09 4d 6f 76 65  20 74 68 65 20 63 6f 6e  |R0..Move the con|
000024d0  74 65 6e 74 73 20 6f 66  20 52 30 20 69 6e 74 6f  |tents of R0 into|
000024e0  20 52 31 32 0a 4d 4f 56  09 52 36 2c 52 36 2c 41  | R12.MOV.R6,R6,A|
000024f0  53 4c 23 32 09 52 36 20  3d 20 52 36 2a 34 0a 4d  |SL#2.R6 = R6*4.M|
00002500  4f 56 09 52 30 2c 52 32  2c 41 53 4c 20 52 35 09  |OV.R0,R2,ASL R5.|
00002510  52 30 20 3d 20 52 32 20  2a 20 28 32 5e 52 35 29  |R0 = R2 * (2^R5)|
00002520  0a 4d 4f 56 45 51 53 09  52 30 2c 52 34 09 09 49  |.MOVEQS.R0,R4..I|
00002530  66 20 5a 20 66 6c 61 67  20 73 65 74 20 54 68 65  |f Z flag set The|
00002540  6e 20 52 30 20 3d 20 52  34 20 28 73 65 74 74 69  |n R0 = R4 (setti|
00002550  6e 67 20 66 6c 61 67 73  29 0a 4d 4f 56 09 52 31  |ng flags).MOV.R1|
00002560  35 2c 52 31 34 09 09 52  65 74 75 72 6e 20 66 72  |5,R14..Return fr|
00002570  6f 6d 20 73 75 62 72 6f  75 74 69 6e 65 0a 23 49  |om subroutine.#I|
00002580  6e 64 65 6e 74 0a 23 77  72 61 70 20 6f 6e 00 00  |ndent.#wrap on..|
00002590  44 41 54 41 a6 02 00 00  4d 56 4e 3a 20 4d 6f 76  |DATA....MVN: Mov|
000025a0  65 20 49 6e 76 65 72 74  65 64 20 44 61 74 61 0a  |e Inverted Data.|
000025b0  23 62 61 63 6b 67 72 6f  75 6e 64 20 77 69 6d 70  |#background wimp|
000025c0  20 31 0a 23 77 72 61 70  20 6f 66 66 0a 53 79 6e  | 1.#wrap off.Syn|
000025d0  74 61 78 3a 20 4d 56 4e  20 5c 7b 5c 3c 73 75 66  |tax: MVN \{\<suf|
000025e0  66 69 78 5c 3e 5c 7d 20  5c 3c 64 65 73 74 69 6e  |fix\>\} \<destin|
000025f0  61 74 69 6f 6e 5c 3e 2c  20 5c 3c 6f 70 65 72 61  |ation\>, \<opera|
00002600  6e 64 32 5c 3e 0a 4f 70  65 72 61 74 69 6f 6e 3a  |nd2\>.Operation:|
00002610  20 64 65 73 74 69 6e 61  74 69 6f 6e 20 3d 20 6e  | destination = n|
00002620  6f 74 20 28 6f 70 65 72  61 6e 64 20 74 77 6f 29  |ot (operand two)|
00002630  0a 46 6c 61 67 73 3a 20  4e 2c 5a 2c 28 43 29 0a  |.Flags: N,Z,(C).|
00002640  23 77 72 61 70 20 6f 6e  0a 23 6c 69 6e 65 0a 54  |#wrap on.#line.T|
00002650  68 69 73 20 69 6e 73 74  72 75 63 74 69 6f 6e 20  |his instruction |
00002660  68 61 73 20 65 78 61 63  74 6c 79 20 74 68 20 73  |has exactly th s|
00002670  61 6d 65 20 65 66 66 65  63 74 20 61 73 20 3c 4d  |ame effect as <M|
00002680  4f 56 3e 2c 20 65 78 63  65 70 74 20 74 68 61 74  |OV>, except that|
00002690  20 61 6c 6c 20 74 68 65  20 62 69 74 73 20 6d 6f  | all the bits mo|
000026a0  76 65 64 20 66 72 6f 6d  20 74 68 65 20 73 6f 75  |ved from the sou|
000026b0  72 63 65 20 72 65 67 69  73 74 65 72 20 61 72 65  |rce register are|
000026c0  20 61 75 74 6f 6d 61 74  69 63 61 6c 6c 79 20 69  | automatically i|
000026d0  6e 76 65 72 74 65 64 2e  20 54 68 69 73 20 61 6c  |nverted. This al|
000026e0  6c 6f 77 73 20 6e 65 67  61 74 69 76 65 20 69 6d  |lows negative im|
000026f0  6d 65 64 69 61 74 65 20  6e 75 6d 62 65 72 73 20  |mediate numbers |
00002700  74 6f 20 62 65 20 6d 6f  76 65 64 20 69 6e 74 6f  |to be moved into|
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00002720  0a 55 6e 64 65 72 20 74  68 65 20 74 77 6f 27 73  |.Under the two's|
00002730  20 63 6f 6d 70 6c 65 6d  65 6e 74 20 73 63 68 65  | complement sche|
00002740  6d 65 2c 20 74 68 65 20  6e 75 6d 62 65 72 20 27  |me, the number '|
00002750  6e 27 20 69 73 20 72 65  70 72 65 73 65 6e 74 65  |n' is represente|
00002760  64 20 61 73 3a 0a 23 49  6e 64 65 6e 74 20 34 0a  |d as:.#Indent 4.|
00002770  4e 4f 54 20 28 6e 29 20  2b 20 31 0a 23 49 6e 64  |NOT (n) + 1.#Ind|
00002780  65 6e 74 0a 23 6c 69 6e  65 0a 45 78 61 6d 70 6c  |ent.#line.Exampl|
00002790  65 73 3a 0a 23 77 72 61  70 20 6f 66 66 0a 23 49  |es:.#wrap off.#I|
000027a0  6e 64 65 6e 74 20 32 0a  4d 56 4e 09 52 30 2c 23  |ndent 2.MVN.R0,#|
000027b0  30 09 09 4d 6f 76 65 20  2d 31 20 69 6e 74 6f 20  |0..Move -1 into |
000027c0  72 65 67 69 73 74 65 72  20 52 30 0a 4d 56 4e 09  |register R0.MVN.|
000027d0  52 31 2c 23 39 09 09 4d  6f 76 65 20 2d 31 30 20  |R1,#9..Move -10 |
000027e0  69 6e 74 6f 20 52 31 0a  4d 56 4e 09 52 33 2c 52  |into R1.MVN.R3,R|
000027f0  35 09 09 52 33 20 3d 20  6e 6f 74 20 28 52 35 29  |5..R3 = not (R5)|
00002800  0a 4d 56 4e 09 52 36 2c  52 37 2c 4c 53 52 20 23  |.MVN.R6,R7,LSR #|
00002810  31 09 52 36 20 3d 20 6e  6f 74 20 28 52 37 20 64  |1.R6 = not (R7 d|
00002820  69 76 20 32 29 0a 23 49  6e 64 65 6e 74 0a 23 77  |iv 2).#Indent.#w|
00002830  72 61 70 20 6f 6e 00 00  44 41 54 41 b8 03 00 00  |rap on..DATA....|
00002840  43 4d 50 3a 20 43 6f 6d  70 61 72 65 0a 23 62 61  |CMP: Compare.#ba|
00002850  63 6b 67 72 6f 75 6e 64  20 77 69 6d 70 20 31 0a  |ckground wimp 1.|
00002860  23 77 72 61 70 20 6f 66  66 0a 53 79 6e 74 61 78  |#wrap off.Syntax|
00002870  3a 20 43 4d 50 20 5c 7b  5c 3c 73 75 66 66 69 78  |: CMP \{\<suffix|
00002880  5c 3e 5c 7d 20 5c 3c 6f  70 65 72 61 6e 64 31 5c  |\>\} \<operand1\|
00002890  3e 2c 20 5c 3c 6f 70 65  72 61 6e 64 32 5c 3e 0a  |>, \<operand2\>.|
000028a0  4f 70 65 72 61 74 69 6f  6e 3a 20 52 65 66 6c 65  |Operation: Refle|
000028b0  63 74 20 72 65 73 75 6c  74 20 6f 66 20 6f 70 65  |ct result of ope|
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000028d0  6e 64 20 74 77 6f 0a 46  6c 61 67 73 3a 20 4e 2c  |nd two.Flags: N,|
000028e0  5a 2c 43 2c 56 0a 23 77  72 61 70 20 6f 6e 0a 23  |Z,C,V.#wrap on.#|
000028f0  6c 69 6e 65 0a 54 68 69  73 20 69 73 20 61 20 76  |line.This is a v|
00002900  65 72 79 20 69 6d 70 6f  72 74 61 6e 74 20 69 6e  |ery important in|
00002910  73 74 72 75 63 74 69 6f  6e 20 63 6f 6e 6e 65 63  |struction connec|
00002920  74 65 64 20 77 69 74 68  20 63 6f 6e 64 69 74 69  |ted with conditi|
00002930  6f 6e 61 6c 20 69 6e 73  74 72 75 63 74 69 6f 6e  |onal instruction|
00002940  20 65 78 65 63 75 74 69  6f 6e 2e 20 54 68 65 20  | execution. The |
00002950  69 6e 73 74 72 75 63 74  69 6f 6e 20 63 6f 6d 70  |instruction comp|
00002960  61 72 65 73 20 74 77 6f  20 6f 70 65 72 61 6e 64  |ares two operand|
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00002980  65 20 73 74 61 74 75 73  20 66 6c 61 67 73 20 64  |e status flags d|
00002990  65 70 65 6e 64 69 6e 67  20 6f 6e 20 74 68 65 20  |epending on the |
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000029c0  6f 70 65 72 61 74 69 6f  6e 20 69 73 20 6e 6f 74  |operation is not|
000029d0  20 73 74 6f 72 65 64 20  61 6e 79 77 68 65 72 65  | stored anywhere|
000029e0  2c 20 77 68 69 63 68 20  65 78 70 6c 61 69 6e 73  |, which explains|
000029f0  20 77 68 79 20 74 68 65  72 65 20 69 73 20 6e 6f  | why there is no|
00002a00  20 6e 65 65 64 20 66 6f  72 20 61 20 64 65 73 74  | need for a dest|
00002a10  69 6e 61 74 69 6f 6e 20  66 69 65 6c 64 2e 20 54  |ination field. T|
00002a20  68 65 20 6f 6e 6c 79 20  74 68 69 6e 67 20 74 6f  |he only thing to|
00002a30  20 72 65 6d 65 6d 62 65  72 20 69 73 20 74 68 61  | remember is tha|
00002a40  74 20 74 68 65 20 76 61  72 69 6f 75 73 20 73 75  |t the various su|
00002a50  62 73 65 71 75 65 6e 74  20 63 6f 6e 64 69 74 69  |bsequent conditi|
00002a60  6f 6e 20 63 6f 64 65 73  20 72 65 66 65 72 20 74  |on codes refer t|
00002a70  6f 20 6f 70 65 72 61 6e  64 20 6f 6e 65 20 63 6f  |o operand one co|
00002a80  6d 70 61 72 65 64 20 77  69 74 68 20 6f 70 65 72  |mpared with oper|
00002a90  61 6e 64 20 74 77 6f 2e  20 54 68 75 73 2c 20 74  |and two. Thus, t|
00002aa0  68 65 20 4c 54 20 28 6c  65 73 73 20 74 68 61 6e  |he LT (less than|
00002ab0  29 20 73 75 66 66 69 78  20 77 69 6c 6c 20 65 78  |) suffix will ex|
00002ac0  65 63 75 74 65 20 69 66  20 6f 70 65 72 61 6e 64  |ecute if operand|
00002ad0  20 6f 6e 65 20 69 73 20  6c 65 73 73 20 74 68 61  | one is less tha|
00002ae0  6e 20 6f 70 65 72 61 6e  64 20 74 77 6f 2e 0a 23  |n operand two..#|
00002af0  6c 69 6e 65 0a 45 78 61  6d 70 6c 65 3a 0a 23 77  |line.Example:.#w|
00002b00  72 61 70 20 6f 66 66 0a  23 69 6e 64 65 6e 74 20  |rap off.#indent |
00002b10  32 0a 43 4d 50 09 52 30  2c 52 31 09 09 43 6f 6d  |2.CMP.R0,R1..Com|
00002b20  70 61 72 65 20 52 30 20  77 69 74 68 20 52 31 0a  |pare R0 with R1.|
00002b30  53 57 49 45 51 09 22 4f  53 5f 4e 65 77 4c 69 6e  |SWIEQ."OS_NewLin|
00002b40  65 22 09 49 66 20 28 52  30 20 2d 20 52 31 20 3d  |e".If (R0 - R1 =|
00002b50  20 30 29 20 65 78 65 63  75 74 65 20 53 57 49 20  | 0) execute SWI |
00002b60  63 6f 6d 6d 61 6e 64 0a  23 69 6e 64 65 6e 74 0a  |command.#indent.|
00002b70  23 77 72 61 70 20 6f 6e  0a 2a 4e 6f 74 65 2a 3a  |#wrap on.*Note*:|
00002b80  20 53 69 6e 63 65 20 74  68 65 20 70 75 72 70 6f  | Since the purpo|
00002b90  73 65 20 6f 66 20 74 68  65 20 43 4d 50 20 69 6e  |se of the CMP in|
00002ba0  73 74 72 75 63 74 69 6f  6e 20 69 73 20 74 6f 20  |struction is to |
00002bb0  61 66 66 65 63 74 20 74  68 65 20 73 74 61 74 75  |affect the statu|
00002bc0  73 20 66 6c 61 67 73 2c  20 74 68 65 20 53 20 73  |s flags, the S s|
00002bd0  75 66 66 69 78 20 64 6f  65 73 20 6e 6f 74 20 68  |uffix does not h|
00002be0  61 76 65 20 74 6f 20 62  65 20 75 73 65 64 2e 0a  |ave to be used..|
00002bf0  44 41 54 41 18 03 00 00  43 4d 4e 3a 20 43 6f 6d  |DATA....CMN: Com|
00002c00  70 61 72 65 20 4e 65 67  61 74 69 76 65 0a 23 62  |pare Negative.#b|
00002c10  61 63 6b 67 72 6f 75 6e  64 20 77 69 6d 70 20 31  |ackground wimp 1|
00002c20  0a 23 77 72 61 70 20 6f  66 66 0a 53 79 6e 74 61  |.#wrap off.Synta|
00002c30  78 3a 20 43 4d 4e 20 5c  7b 5c 3c 73 75 66 66 69  |x: CMN \{\<suffi|
00002c40  78 5c 3e 5c 7d 20 5c 3c  6f 70 65 72 61 6e 64 31  |x\>\} \<operand1|
00002c50  5c 3e 2c 20 5c 3c 6f 70  65 72 61 6e 64 32 5c 3e  |\>, \<operand2\>|
00002c60  0a 4f 70 65 72 61 74 69  6f 6e 3a 20 52 65 66 6c  |.Operation: Refl|
00002c70  65 63 74 20 72 65 73 75  6c 74 20 6f 66 20 6f 70  |ect result of op|
00002c80  65 72 61 6e 64 20 6f 6e  65 20 2d 20 28 2d 20 6f  |erand one - (- o|
00002c90  70 65 72 61 6e 64 20 74  77 6f 29 0a 46 6c 61 67  |perand two).Flag|
00002ca0  73 3a 20 4e 2c 5a 2c 43  2c 56 0a 23 77 72 61 70  |s: N,Z,C,V.#wrap|
00002cb0  20 6f 6e 0a 23 6c 69 6e  65 0a 43 4d 4e 20 69 73  | on.#line.CMN is|
00002cc0  20 65 78 61 63 74 6c 79  20 74 68 65 20 73 61 6d  | exactly the sam|
00002cd0  65 20 61 73 20 3c 43 4d  50 3e 2c 20 65 78 63 65  |e as <CMP>, exce|
00002ce0  70 74 20 74 68 61 74 20  69 74 20 63 6f 6d 70 61  |pt that it compa|
00002cf0  72 65 73 20 6f 70 65 72  61 6e 64 20 6f 6e 65 20  |res operand one |
00002d00  77 69 74 68 20 74 68 65  20 6e 65 67 61 74 69 76  |with the negativ|
00002d10  65 20 6f 66 20 6f 70 65  72 61 6e 64 20 74 77 6f  |e of operand two|
00002d20  2e 0a 23 6c 69 6e 65 0a  54 68 69 73 20 69 6e 73  |..#line.This ins|
00002d30  74 72 75 63 74 69 6f 6e  20 61 6c 6c 6f 77 73 20  |truction allows |
00002d40  63 6f 6d 70 61 72 69 73  6f 6e 73 20 74 6f 20 62  |comparisons to b|
00002d50  65 20 6d 61 64 65 20 77  69 74 68 20 73 6d 61 6c  |e made with smal|
00002d60  6c 20 69 6d 6d 65 64 69  61 74 65 20 63 6f 6e 73  |l immediate cons|
00002d70  74 61 6e 74 73 20 77 68  69 63 68 20 63 6f 75 6c  |tants which coul|
00002d80  64 20 6e 6f 74 20 62 65  20 72 65 70 72 65 73 65  |d not be represe|
00002d90  6e 74 65 64 20 6f 74 68  65 72 77 69 73 65 2e 20  |nted otherwise. |
00002da0  54 68 65 20 41 52 4d 20  77 69 6c 6c 20 61 75 74  |The ARM will aut|
00002db0  6f 6d 61 74 69 63 61 6c  6c 79 20 66 6f 72 6d 20  |omatically form |
00002dc0  74 68 65 20 6e 65 67 61  74 69 76 65 20 6f 66 20  |the negative of |
00002dd0  6f 70 65 72 61 6e 64 20  74 77 6f 20 61 6e 64 20  |operand two and |
00002de0  74 68 65 6e 20 6d 61 6b  65 20 74 68 65 20 63 6f  |then make the co|
00002df0  6d 70 61 72 69 73 6f 6e  2e 0a 23 6c 69 6e 65 0a  |mparison..#line.|
00002e00  45 78 61 6d 70 6c 65 73  0a 23 77 72 61 70 20 6f  |Examples.#wrap o|
00002e10  66 66 0a 23 69 6e 64 65  6e 74 20 32 0a 43 4d 4e  |ff.#indent 2.CMN|
00002e20  09 52 35 2c 52 37 09 09  43 6f 6d 70 61 72 65 20  |.R5,R7..Compare |
00002e30  52 35 20 77 69 74 68 20  2d 52 37 0a 43 4d 4e 09  |R5 with -R7.CMN.|
00002e40  52 36 2c 23 31 09 09 43  6f 6d 70 61 72 65 20 52  |R6,#1..Compare R|
00002e50  36 20 77 69 74 68 20 2d  31 0a 43 4d 4e 09 52 33  |6 with -1.CMN.R3|
00002e60  2c 52 30 2c 4c 53 4c 23  31 09 43 6f 6d 70 61 72  |,R0,LSL#1.Compar|
00002e70  65 20 52 33 20 77 69 74  68 20 2d 52 30 2a 32 0a  |e R3 with -R0*2.|
00002e80  23 69 6e 64 65 6e 74 0a  23 77 72 61 70 20 6f 6e  |#indent.#wrap on|
00002e90  0a 2a 4e 6f 74 65 2a 3a  20 53 69 6e 63 65 20 74  |.*Note*: Since t|
00002ea0  68 65 20 70 75 72 70 6f  73 65 20 6f 66 20 74 68  |he purpose of th|
00002eb0  65 20 43 4d 50 20 69 6e  73 74 72 75 63 74 69 6f  |e CMP instructio|
00002ec0  6e 20 69 73 20 74 6f 20  61 66 66 65 63 74 20 74  |n is to affect t|
00002ed0  68 65 20 73 74 61 74 75  73 20 66 6c 61 67 73 2c  |he status flags,|
00002ee0  20 74 68 65 20 53 20 73  75 66 66 69 78 20 64 6f  | the S suffix do|
00002ef0  65 73 20 6e 6f 74 20 68  61 76 65 20 74 6f 20 62  |es not have to b|
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00003d10  79 6e 74 61 78 3a 20 54  45 51 20 5c 7b 5c 3c 73  |yntax: TEQ \{\<s|
00003d20  75 66 66 69 78 5c 3e 5c  7d 20 5c 3c 6f 70 65 72  |uffix\>\} \<oper|
00003d30  61 6e 64 31 5c 3e 2c 20  5c 3c 6f 70 65 72 61 6e  |and1\>, \<operan|
00003d40  64 32 5c 3e 0a 4f 70 65  72 61 74 69 6f 6e 3a 20  |d2\>.Operation: |
00003d50  52 65 66 6c 65 63 74 20  72 65 73 75 6c 74 20 6f  |Reflect result o|
00003d60  66 20 6f 70 65 72 61 6e  64 20 6f 6e 65 20 45 4f  |f operand one EO|
00003d70  52 20 6f 70 65 72 61 6e  64 20 74 77 6f 0a 46 6c  |R operand two.Fl|
00003d80  61 67 73 3a 20 4e 2c 5a  2c 28 43 29 0a 23 77 72  |ags: N,Z,(C).#wr|
00003d90  61 70 20 6f 6e 0a 23 6c  69 6e 65 0a 54 68 69 73  |ap on.#line.This|
00003da0  20 69 6e 73 74 72 75 63  74 69 6f 6e 20 69 73 20  | instruction is |
00003db0  76 65 72 79 20 73 69 6d  69 6c 61 72 20 74 6f 20  |very similar to |
00003dc0  3c 54 53 54 3e 2e 20 54  68 65 20 6f 6e 6c 79 20  |<TST>. The only |
00003dd0  64 69 66 66 65 72 65 6e  63 65 20 69 73 20 74 68  |difference is th|
00003de0  61 74 20 69 74 20 70 65  72 66 6f 72 6d 73 20 61  |at it performs a|
00003df0  20 6e 6f 74 69 6f 6e 61  6c 20 45 4f 52 20 6f 70  | notional EOR op|
00003e00  65 72 61 74 69 6f 6e 20  62 65 74 77 65 65 6e 20  |eration between |
00003e10  69 74 73 20 6f 70 65 72  61 6e 64 73 2c 20 69 6e  |its operands, in|
00003e20  73 74 65 61 64 20 6f 66  20 61 6e 20 41 4e 44 2e  |stead of an AND.|
00003e30  20 54 68 65 20 54 45 51  20 69 6e 73 74 72 75 63  | The TEQ instruc|
00003e40  74 69 6f 6e 20 63 61 6e  20 62 65 20 75 73 65 64  |tion can be used|
00003e50  20 74 6f 20 73 65 65 20  69 66 20 74 68 65 20 62  | to see if the b|
00003e60  69 74 73 20 69 6e 20 74  77 6f 20 64 61 74 61 20  |its in two data |
00003e70  77 6f 72 64 73 20 61 72  65 20 74 68 65 20 73 61  |words are the sa|
00003e80  6d 65 20 6f 72 20 6e 6f  74 2e 0a 23 6c 69 6e 65  |me or not..#line|
00003e90  0a 54 68 69 73 20 63 6f  6d 70 61 72 69 73 6f 6e  |.This comparison|
00003ea0  20 77 6f 75 6c 64 20 6e  6f 72 6d 61 6c 6c 79 20  | would normally |
00003eb0  62 65 20 70 65 72 66 6f  72 6d 65 64 20 75 73 69  |be performed usi|
00003ec0  6e 67 20 3c 43 4d 50 3e  2e 20 48 6f 77 65 76 65  |ng <CMP>. Howeve|
00003ed0  72 20 54 45 51 20 64 6f  65 73 20 6e 6f 74 20 61  |r TEQ does not a|
00003ee0  66 66 65 63 74 20 74 68  65 20 63 61 72 72 79 20  |ffect the carry |
00003ef0  66 6c 61 67 2c 20 77 68  69 63 68 20 6d 61 79 20  |flag, which may |
00003f00  73 6f 6d 65 74 69 6d 65  73 20 62 65 20 75 73 65  |sometimes be use|
00003f10  66 75 6c 2e 0a 23 6c 69  6e 65 0a 45 78 61 6d 70  |ful..#line.Examp|
00003f20  6c 65 73 3a 0a 23 77 72  61 70 20 6f 66 66 0a 23  |les:.#wrap off.#|
00003f30  49 6e 64 65 6e 74 20 32  0a 54 45 51 09 52 31 2c  |Indent 2.TEQ.R1,|
00003f40  23 35 09 09 54 65 73 74  20 74 6f 20 73 65 65 20  |#5..Test to see |
00003f50  69 66 20 52 31 20 63 6f  6e 74 61 69 6e 73 20 35  |if R1 contains 5|
00003f60  0a 54 45 51 09 52 33 2c  52 34 09 09 54 65 73 74  |.TEQ.R3,R4..Test|
00003f70  20 74 6f 20 73 65 65 20  69 66 20 52 33 20 3d 20  | to see if R3 = |
00003f80  52 34 0a 23 49 6e 64 65  6e 74 0a 23 77 72 61 70  |R4.#Indent.#wrap|
00003f90  20 6f 6e 0a 2a 4e 6f 74  65 2a 3a 20 54 68 69 73  | on.*Note*: This|
00003fa0  20 69 73 20 61 6e 6f 74  68 65 72 20 69 6e 73 74  | is another inst|
00003fb0  72 75 63 74 69 6f 6e 20  77 68 65 72 65 20 74 68  |ruction where th|
00003fc0  65 20 53 20 73 75 66 66  69 78 20 69 73 20 69 6d  |e S suffix is im|
00003fd0  70 6c 69 65 64 2e 00 00  44 41 54 41 6b 03 00 00  |plied...DATAk...|
00003fe0  4d 4c 41 3a 20 4d 75 6c  74 69 70 6c 69 63 61 74  |MLA: Multiplicat|
00003ff0  69 6f 6e 20 77 69 74 68  20 41 63 63 75 6d 75 6c  |ion with Accumul|
00004000  61 74 65 0a 23 62 61 63  6b 67 72 6f 75 6e 64 20  |ate.#background |
00004010  77 69 6d 70 20 31 0a 23  77 72 61 70 20 6f 66 66  |wimp 1.#wrap off|
00004020  0a 53 79 6e 74 61 78 3a  20 4d 4c 41 20 5c 7b 5c  |.Syntax: MLA \{\|
00004030  3c 73 75 66 66 69 78 5c  3e 5c 7d 20 5c 3c 64 65  |<suffix\>\} \<de|
00004040  73 74 69 6e 61 74 69 6f  6e 5c 3e 2c 20 5c 3c 6f  |stination\>, \<o|
00004050  70 65 72 61 6e 64 31 5c  3e 2c 20 5c 3c 6f 70 65  |perand1\>, \<ope|
00004060  72 61 6e 64 32 5c 3e 2c  20 5c 3c 73 75 6d 5c 3e  |rand2\>, \<sum\>|
00004070  0a 4f 70 65 72 61 74 69  6f 6e 3a 20 64 65 73 74  |.Operation: dest|
00004080  69 6e 61 74 69 6f 6e 20  3d 20 28 6f 70 65 72 61  |ination = (opera|
00004090  6e 64 20 6f 6e 65 20 2a  20 6f 70 65 72 61 6e 64  |nd one * operand|
000040a0  20 74 77 6f 29 20 2b 20  73 75 6d 0a 46 6c 61 67  | two) + sum.Flag|
000040b0  73 3a 20 4e 2c 5a 20 5b  56 20 2d 20 75 6e 63 68  |s: N,Z [V - unch|
000040c0  61 6e 67 65 64 3b 20 43  20 2d 20 75 6e 64 65 66  |anged; C - undef|
000040d0  69 6e 65 64 5d 0a 23 77  72 61 70 20 6f 6e 0a 23  |ined].#wrap on.#|
000040e0  6c 69 6e 65 0a 54 68 69  73 20 69 6e 73 74 72 75  |line.This instru|
000040f0  63 74 69 6f 6e 20 69 73  20 73 69 6d 69 6c 61 72  |ction is similar|
00004100  20 74 6f 20 3c 4d 55 4c  3e 2c 20 74 68 65 20 64  | to <MUL>, the d|
00004110  69 66 66 65 72 65 6e 63  65 20 62 65 69 6e 67 20  |ifference being |
00004120  74 68 61 74 20 74 68 65  20 63 6f 6e 74 65 6e 74  |that the content|
00004130  73 20 6f 66 20 74 68 65  20 72 65 67 69 73 74 65  |s of the registe|
00004140  72 20 67 69 76 65 6e 20  69 6e 20 74 68 65 20 73  |r given in the s|
00004150  75 6d 20 66 69 65 6c 64  20 61 72 65 20 61 64 64  |um field are add|
00004160  65 64 20 69 6e 74 6f 20  74 68 65 20 72 65 73 75  |ed into the resu|
00004170  6c 74 20 6f 66 20 74 68  65 20 6d 75 6c 74 69 70  |lt of the multip|
00004180  6c 69 63 61 74 69 6f 6e  20 62 65 66 6f 72 65 20  |lication before |
00004190  73 74 6f 72 69 6e 67 20  69 74 20 69 6e 20 74 68  |storing it in th|
000041a0  65 20 64 65 73 74 69 6e  61 74 69 6f 6e 20 72 65  |e destination re|
000041b0  67 69 73 74 65 72 2e 20  54 68 65 20 72 65 73 74  |gister. The rest|
000041c0  72 69 63 74 69 6f 6e 73  20 77 68 69 63 68 20 61  |rictions which a|
000041d0  70 70 6c 79 20 74 6f 20  3c 4d 55 4c 3e 20 61 6c  |pply to <MUL> al|
000041e0  73 6f 20 61 70 70 6c 79  20 74 6f 20 4d 4c 41 2e  |so apply to MLA.|
000041f0  0a 23 6c 69 6e 65 0a 4d  4c 41 20 69 73 20 75 73  |.#line.MLA is us|
00004200  65 64 20 74 6f 20 6b 65  65 70 20 61 20 72 75 6e  |ed to keep a run|
00004210  6e 69 6e 67 20 74 6f 74  61 6c 20 6f 66 20 61 20  |ning total of a |
00004220  73 65 72 69 65 73 20 6f  66 20 6d 75 6c 74 69 70  |series of multip|
00004230  6c 69 63 61 74 69 6f 6e  73 2e 20 49 66 20 74 68  |lications. If th|
00004240  65 20 73 75 6d 20 72 65  67 69 73 74 65 72 20 69  |e sum register i|
00004250  73 20 73 70 65 63 69 66  69 65 64 20 61 73 20 62  |s specified as b|
00004260  65 69 6e 67 20 74 68 65  20 73 61 6d 65 20 61 73  |eing the same as|
00004270  20 74 68 65 20 64 65 73  74 69 6e 61 74 69 6f 6e  | the destination|
00004280  2c 20 74 68 65 6e 20 74  68 65 20 72 65 73 75 6c  |, then the resul|
00004290  74 20 6f 66 20 65 61 63  68 20 6d 75 6c 74 69 70  |t of each multip|
000042a0  6c 69 63 61 74 69 6f 6e  20 77 69 6c 6c 20 62 65  |lication will be|
000042b0  20 61 63 63 75 6d 75 6c  61 74 65 64 20 69 6e 20  | accumulated in |
000042c0  74 68 65 20 64 65 73 74  69 6e 61 74 69 6f 6e 20  |the destination |
000042d0  72 65 67 69 73 74 65 72  2e 0a 23 6c 69 6e 65 0a  |register..#line.|
000042e0  45 78 61 6d 70 6c 65 73  3a 0a 23 49 6e 64 65 6e  |Examples:.#Inden|
000042f0  74 20 32 0a 4d 4c 41 09  52 30 2c 52 31 2c 52 32  |t 2.MLA.R0,R1,R2|
00004300  2c 52 33 09 52 30 20 3d  20 28 52 31 20 2a 20 52  |,R3.R0 = (R1 * R|
00004310  32 29 20 2b 20 52 33 0a  4d 4c 41 09 52 30 2c 52  |2) + R3.MLA.R0,R|
00004320  31 2c 52 32 2c 52 30 09  52 30 20 3d 20 28 52 31  |1,R2,R0.R0 = (R1|
00004330  20 2a 20 52 32 29 20 2b  20 52 30 0a 23 49 6e 64  | * R2) + R0.#Ind|
00004340  65 6e 74 00 44 41 54 41  c0 02 00 00 4d 55 4c 3a  |ent.DATA....MUL:|
00004350  20 4d 75 6c 74 69 70 6c  69 63 61 74 69 6f 6e 0a  | Multiplication.|
00004360  23 62 61 63 6b 67 72 6f  75 6e 64 20 77 69 6d 70  |#background wimp|
00004370  20 31 0a 23 77 72 61 70  20 6f 66 66 0a 53 79 6e  | 1.#wrap off.Syn|
00004380  74 61 78 3a 20 4d 55 4c  20 5c 7b 5c 3c 73 75 66  |tax: MUL \{\<suf|
00004390  66 69 78 5c 3e 5c 7d 20  5c 3c 64 65 73 74 69 6e  |fix\>\} \<destin|
000043a0  61 74 69 6f 6e 5c 3e 2c  20 5c 3c 6f 70 65 72 61  |ation\>, \<opera|
000043b0  6e 64 31 5c 3e 2c 20 5c  3c 6f 70 65 72 61 6e 64  |nd1\>, \<operand|
000043c0  32 5c 3e 0a 4f 70 65 72  61 74 69 6f 6e 3a 20 64  |2\>.Operation: d|
000043d0  65 73 74 69 6e 61 74 69  6f 6e 20 3d 20 6f 70 65  |estination = ope|
000043e0  72 61 6e 64 20 6f 6e 65  20 2a 20 6f 70 65 72 61  |rand one * opera|
000043f0  6e 64 20 74 77 6f 0a 46  6c 61 67 73 3a 20 4e 2c  |nd two.Flags: N,|
00004400  5a 20 5b 56 20 2d 20 75  6e 63 68 61 6e 67 65 64  |Z [V - unchanged|
00004410  3b 20 43 20 2d 20 75 6e  64 65 66 69 6e 65 64 5d  |; C - undefined]|
00004420  0a 23 77 72 61 70 20 6f  6e 0a 23 6c 69 6e 65 0a  |.#wrap on.#line.|
00004430  54 68 69 73 20 69 6e 73  74 72 75 63 74 69 6f 6e  |This instruction|
00004440  20 70 65 72 66 6f 72 6d  73 20 33 32 2d 62 69 74  | performs 32-bit|
00004450  20 6d 75 6c 74 69 70 6c  69 63 61 74 69 6f 6e 20  | multiplication |
00004460  6f 66 20 74 68 65 20 74  77 6f 20 6f 70 65 72 61  |of the two opera|
00004470  6e 64 73 2c 20 77 69 74  68 20 74 68 65 20 72 65  |nds, with the re|
00004480  73 75 6c 74 20 62 65 69  6e 67 20 73 74 6f 72 65  |sult being store|
00004490  64 20 69 6e 20 74 68 65  20 64 65 73 74 69 6e 61  |d in the destina|
000044a0  74 69 6f 6e 20 72 65 67  69 73 74 65 72 2e 0a 23  |tion register..#|
000044b0  6c 69 6e 65 0a 54 68 65  72 65 20 61 72 65 20 63  |line.There are c|
000044c0  65 72 74 61 69 6e 20 72  65 73 74 72 69 63 74 69  |ertain restricti|
000044d0  6f 6e 73 20 61 73 73 6f  63 69 61 74 65 64 20 77  |ons associated w|
000044e0  69 74 68 20 74 68 65 20  75 73 65 20 6f 66 20 74  |ith the use of t|
000044f0  68 69 73 20 69 6e 73 74  72 75 63 74 69 6f 6e 3a  |his instruction:|
00004500  0a 23 77 72 61 70 20 6f  66 66 0a 23 49 6e 64 65  |.#wrap off.#Inde|
00004510  6e 74 20 32 0a 2d 20 54  68 65 20 33 20 64 61 74  |nt 2.- The 3 dat|
00004520  61 20 66 69 65 6c 64 73  20 73 70 65 63 69 66 69  |a fields specifi|
00004530  65 64 20 6d 75 73 74 20  62 65 20 73 69 6d 70 6c  |ed must be simpl|
00004540  65 20 72 65 67 69 73 74  65 72 73 0a 2d 20 54 68  |e registers.- Th|
00004550  65 20 64 65 73 74 69 6e  61 74 69 6f 6e 20 61 6e  |e destination an|
00004560  64 20 6f 70 65 72 61 6e  64 31 20 6d 75 73 74 20  |d operand1 must |
00004570  62 65 20 64 69 66 66 65  72 65 6e 74 20 72 65 67  |be different reg|
00004580  69 73 74 65 72 73 0a 2d  20 52 31 35 20 6d 61 79  |isters.- R15 may|
00004590  20 6e 6f 74 20 62 65 20  75 73 65 64 20 61 73 20  | not be used as |
000045a0  74 68 65 20 64 65 73 74  69 6e 61 74 69 6f 6e 20  |the destination |
000045b0  72 65 67 69 73 74 65 72  0a 23 49 6e 64 65 6e 74  |register.#Indent|
000045c0  0a 23 77 72 61 70 20 6f  6e 0a 23 6c 69 6e 65 0a  |.#wrap on.#line.|
000045d0  45 78 61 6d 70 6c 65 3a  0a 23 49 6e 64 65 6e 74  |Example:.#Indent|
000045e0  20 32 0a 4d 55 4c 09 52  30 2c 52 31 2c 52 33 09  | 2.MUL.R0,R1,R3.|
000045f0  52 30 20 3d 20 52 31 20  2a 20 52 33 0a 23 49 6e  |R0 = R1 * R3.#In|
00004600  64 65 6e 74 44 41 54 41  b3 02 00 00 53 57 49 3a  |dentDATA....SWI:|
00004610  20 53 6f 66 74 77 61 72  65 20 49 6e 74 65 72 72  | Software Interr|
00004620  75 70 74 0a 23 62 61 63  6b 67 72 6f 75 6e 64 20  |upt.#background |
00004630  77 69 6d 70 20 31 0a 23  77 72 61 70 20 6f 66 66  |wimp 1.#wrap off|
00004640  0a 53 79 6e 74 61 78 3a  20 53 57 49 20 5c 3c 61  |.Syntax: SWI \<a|
00004650  72 67 75 6d 65 6e 74 5c  3e 20 0a 23 77 72 61 70  |rgument\> .#wrap|
00004660  20 6f 6e 0a 23 6c 69 6e  65 0a 57 68 65 6e 20 65  | on.#line.When e|
00004670  78 65 63 75 74 65 64 2c  20 74 68 69 73 20 69 6e  |xecuted, this in|
00004680  73 74 72 75 63 74 69 6f  6e 20 63 61 75 73 65 73  |struction causes|
00004690  20 74 68 65 20 70 72 6f  63 65 73 73 6f 72 20 74  | the processor t|
000046a0  6f 20 62 72 65 61 6b 20  6f 66 66 20 66 72 6f 6d  |o break off from|
000046b0  20 74 68 65 20 63 75 72  72 65 6e 74 20 70 72 6f  | the current pro|
000046c0  67 72 61 6d 2e 20 54 68  65 20 41 52 4d 20 73 77  |gram. The ARM sw|
000046d0  69 74 63 68 65 73 20 69  6e 74 6f 20 73 75 70 65  |itches into supe|
000046e0  72 76 69 73 6f 72 20 6d  6f 64 65 20 61 6e 64 20  |rvisor mode and |
000046f0  6a 75 6d 70 73 20 74 6f  20 61 20 70 72 65 2d 64  |jumps to a pre-d|
00004700  65 66 69 6e 65 64 20 61  64 64 72 65 73 73 20 69  |efined address i|
00004710  6e 20 74 68 65 20 4f 53  2e 20 54 68 65 20 61 72  |n the OS. The ar|
00004720  67 75 6d 65 6e 74 20 66  69 65 6c 64 20 69 73 20  |gument field is |
00004730  74 68 65 6e 20 65 78 61  6d 69 6e 65 64 20 74 6f  |then examined to|
00004740  20 64 65 74 65 72 6d 69  6e 65 20 77 68 69 63 68  | determine which|
00004750  20 6f 66 20 74 68 65 20  6d 61 6e 79 20 4f 53 20  | of the many OS |
00004760  66 61 63 69 6c 69 74 69  65 73 20 68 61 73 20 62  |facilities has b|
00004770  65 65 6e 20 72 65 71 75  65 73 74 65 64 2e 20 57  |een requested. W|
00004780  68 65 6e 20 74 68 65 20  61 70 70 72 6f 70 72 69  |hen the appropri|
00004790  61 74 65 20 72 6f 75 74  69 6e 65 20 68 61 73 20  |ate routine has |
000047a0  62 65 65 6e 20 63 6f 6d  70 6c 65 74 65 64 2c 20  |been completed, |
000047b0  74 68 65 20 41 52 4d 20  72 65 73 75 6d 65 73 20  |the ARM resumes |
000047c0  74 68 65 20 65 78 65 63  75 74 69 6f 6e 20 6f 66  |the execution of|
000047d0  20 74 68 65 20 75 73 65  72 20 70 72 6f 67 72 61  | the user progra|
000047e0  6d 20 77 68 65 72 65 20  69 74 20 6c 65 66 74 20  |m where it left |
000047f0  6f 66 66 2e 0a 23 6c 69  6e 65 0a 45 78 61 6d 70  |off..#line.Examp|
00004800  6c 65 73 3a 0a 23 49 6e  64 65 6e 74 20 32 0a 53  |les:.#Indent 2.S|
00004810  57 49 09 22 4f 53 5f 4d  6f 75 73 65 22 0a 53 57  |WI."OS_Mouse".SW|
00004820  49 09 22 57 69 6d 70 5f  43 72 65 61 74 65 57 69  |I."Wimp_CreateWi|
00004830  6e 64 6f 77 22 0a 23 49  6e 64 65 6e 74 0a 2a 4e  |ndow".#Indent.*N|
00004840  6f 74 65 2a 3a 20 54 68  65 20 6e 61 6d 65 20 6f  |ote*: The name o|
00004850  66 20 74 68 65 20 72 6f  75 74 69 6e 65 20 6d 75  |f the routine mu|
00004860  73 74 20 6d 61 74 63 68  20 75 70 20 77 69 74 68  |st match up with|
00004870  20 74 68 61 74 20 72 65  63 6f 67 6e 69 73 65 64  | that recognised|
00004880  20 62 79 20 74 68 65 20  61 73 73 65 6d 62 6c 65  | by the assemble|
00004890  72 20 69 6e 63 6c 75 64  69 6e 67 20 74 68 65 20  |r including the |
000048a0  63 61 73 65 20 6f 66 20  65 61 63 68 20 63 68 61  |case of each cha|
000048b0  72 61 63 74 65 72 2e 00  44 41 54 41 47 02 00 00  |racter..DATAG...|
000048c0  42 3a 20 53 69 6d 70 6c  65 20 42 72 61 6e 63 68  |B: Simple Branch|
000048d0  0a 23 62 61 63 6b 67 72  6f 75 6e 64 20 77 69 6d  |.#background wim|
000048e0  70 20 31 0a 23 77 72 61  70 20 6f 66 66 0a 53 79  |p 1.#wrap off.Sy|
000048f0  6e 74 61 78 3a 20 42 20  5c 3c 61 64 64 72 65 73  |ntax: B \<addres|
00004900  73 5c 3e 0a 4f 70 65 72  61 74 69 6f 6e 3a 20 4a  |s\>.Operation: J|
00004910  75 6d 70 20 74 6f 20 73  70 65 63 69 66 69 65 64  |ump to specified|
00004920  20 61 64 64 72 65 73 73  0a 23 77 72 61 70 20 6f  | address.#wrap o|
00004930  6e 0a 23 6c 69 6e 65 0a  54 68 69 73 20 69 6e 73  |n.#line.This ins|
00004940  74 72 75 63 74 69 6f 6e  20 69 73 20 61 6e 61 6c  |truction is anal|
00004950  6f 67 6f 75 73 20 74 6f  20 74 68 65 20 42 41 53  |ogous to the BAS|
00004960  49 43 20 47 4f 54 4f 20  73 74 61 74 65 6d 65 6e  |IC GOTO statemen|
00004970  74 20 2d 20 69 74 20 6d  61 6b 65 73 20 74 68 65  |t - it makes the|
00004980  20 70 72 6f 63 65 73 73  6f 72 20 62 72 65 61 6b  | processor break|
00004990  20 6f 66 66 20 66 72 6f  6d 20 69 74 73 20 6e 6f  | off from its no|
000049a0  72 6d 61 6c 20 73 65 71  75 65 6e 74 69 61 6c 20  |rmal sequential |
000049b0  65 78 65 63 75 74 69 6f  6e 20 6f 66 20 69 6e 73  |execution of ins|
000049c0  74 72 75 63 74 69 6f 6e  73 20 61 6e 64 20 6a 75  |tructions and ju|
000049d0  6d 70 20 74 6f 20 61 20  6e 65 77 20 69 6e 73 74  |mp to a new inst|
000049e0  72 75 63 74 69 6f 6e 20  61 74 20 61 20 64 65 73  |ruction at a des|
000049f0  69 67 6e 61 74 65 64 20  6c 6f 63 61 74 69 6f 6e  |ignated location|
00004a00  2e 0a 23 6c 69 6e 65 0a  57 68 65 6e 20 75 73 65  |..#line.When use|
00004a10  64 20 69 6e 20 63 6f 6e  6a 75 6e 63 74 69 6f 6e  |d in conjunction|
00004a20  20 77 69 74 68 20 74 68  65 20 6e 6f 72 6d 61 6c  | with the normal|
00004a30  20 63 6f 6e 64 69 74 69  6f 6e 20 63 6f 64 65 73  | condition codes|
00004a40  2c 20 74 68 69 73 20 69  6e 73 74 72 75 63 74 69  |, this instructi|
00004a50  6f 6e 20 62 65 63 6f 6d  65 73 20 74 68 65 20 62  |on becomes the b|
00004a60  61 73 69 73 20 6f 66 20  63 6f 6e 64 69 74 69 6f  |asis of conditio|
00004a70  6e 61 6c 20 62 72 61 6e  63 68 69 6e 67 2e 0a 23  |nal branching..#|
00004a80  6c 69 6e 65 0a 45 78 61  6d 70 6c 65 3a 0a 23 49  |line.Example:.#I|
00004a90  6e 64 65 6e 74 20 32 0a  2e 6c 6f 6f 70 0a 53 55  |ndent 2..loop.SU|
00004aa0  42 09 52 30 2c 52 30 2c  23 31 09 52 30 20 3d 20  |B.R0,R0,#1.R0 = |
00004ab0  52 30 20 2d 20 31 0a 43  4d 50 09 52 30 2c 23 30  |R0 - 1.CMP.R0,#0|
00004ac0  09 09 69 73 20 52 30 20  3d 20 30 3f 0a 42 4e 45  |..is R0 = 0?.BNE|
00004ad0  09 6c 6f 6f 70 09 09 69  66 20 6e 6f 74 2c 20 67  |.loop..if not, g|
00004ae0  6f 20 62 61 63 6b 20 74  6f 20 73 74 61 72 74 20  |o back to start |
00004af0  6f 66 20 6c 6f 6f 70 0a  23 49 6e 64 65 6e 74 00  |of loop.#Indent.|
00004b00  44 41 54 41 b6 04 00 00  42 4c 3a 20 42 72 61 6e  |DATA....BL: Bran|
00004b10  63 68 20 77 69 74 68 20  4c 69 6e 6b 0a 23 62 61  |ch with Link.#ba|
00004b20  63 6b 67 72 6f 75 6e 64  20 77 69 6d 70 20 31 0a  |ckground wimp 1.|
00004b30  23 77 72 61 70 20 6f 66  66 0a 53 79 6e 74 61 78  |#wrap off.Syntax|
00004b40  3a 20 42 4c 20 5c 3c 61  64 64 72 65 73 73 5c 3e  |: BL \<address\>|
00004b50  0a 4f 70 65 72 61 74 69  6f 6e 3a 20 5b 4d 4f 56  |.Operation: [MOV|
00004b60  20 52 31 34 2c 50 43 5d  20 2b 20 4a 75 6d 70 20  | R14,PC] + Jump |
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00004bc0  4f 53 55 42 20 73 74 61  74 65 6d 65 6e 74 20 2d  |OSUB statement -|
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00004ca0  6f 72 69 67 69 6e 61 6c  20 42 72 61 6e 63 68 20  |original Branch |
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00004d50  20 32 0a 2e 6c 6f 6f 70  0a 53 55 42 09 52 30 2c  | 2..loop.SUB.R0,|
00004d60  52 30 2c 23 31 09 52 30  20 3d 20 52 30 20 2d 20  |R0,#1.R0 = R0 - |
00004d70  31 0a 43 4d 50 09 52 30  2c 23 30 09 09 69 73 20  |1.CMP.R0,#0..is |
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00004da0  6b 20 74 6f 20 73 74 61  72 74 20 6f 66 20 6c 6f  |k to start of lo|
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00004dc0  09 6f 74 68 65 72 77 69  73 65 2c 20 67 6f 20 74  |.otherwise, go t|
00004dd0  6f 20 73 75 62 72 6f 75  74 69 6e 65 0a 2e 2e 2e  |o subroutine....|
00004de0  0a 2e 73 75 62 72 6f 75  74 69 6e 65 0a 4d 4f 56  |..subroutine.MOV|
00004df0  20 50 43 2c 52 31 34 09  09 72 65 74 75 72 6e 20  | PC,R14..return |
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00004e10  64 65 6e 74 0a 23 6c 69  6e 65 3b 20 77 72 61 70  |dent.#line; wrap|
00004e20  20 6e 6f 6a 6f 69 6e 0a  2a 4e 6f 74 65 2a 3a 20  | nojoin.*Note*: |
00004e30  49 74 20 69 73 20 69 6d  70 6f 72 74 61 6e 74 20  |It is important |
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00004e60  72 65 64 20 65 6c 73 65  77 68 65 72 65 20 70 72  |red elsewhere pr|
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00004e90  68 69 73 20 63 61 6e 20  62 65 20 64 6f 6e 65 20  |his can be done |
00004ea0  75 73 69 6e 67 20 61 20  3c 73 74 61 63 6b 3d 3e  |using a <stack=>|
00004eb0  73 74 61 63 6b 73 3e 2e  0a 54 68 65 20 63 6f 6d  |stacks>..The com|
00004ec0  6d 61 6e 64 20 27 4d 4f  56 20 50 43 2c 52 31 34  |mand 'MOV PC,R14|
00004ed0  27 20 77 69 6c 6c 20 6d  65 61 6e 20 74 68 61 74  |' will mean that|
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00004ef0  61 74 75 73 20 66 6c 61  67 20 73 65 74 74 69 6e  |atus flag settin|
00004f00  67 73 20 77 69 6c 6c 20  6e 6f 74 20 62 65 20 72  |gs will not be r|
00004f10  65 73 74 6f 72 65 64 20  6f 6e 63 65 20 74 68 65  |estored once the|
00004f20  20 73 75 62 72 6f 75 74  69 6e 65 20 68 61 73 20  | subroutine has |
00004f30  72 65 74 75 72 6e 65 64  2e 20 53 68 6f 75 6c 64  |returned. Should|
00004f40  20 74 68 65 20 75 73 65  72 20 77 61 6e 74 20 74  | the user want t|
00004f50  68 65 20 66 6c 61 67 73  20 74 6f 20 62 65 20 75  |he flags to be u|
00004f60  6e 61 66 66 65 63 74 65  64 20 62 79 20 74 68 65  |naffected by the|
00004f70  20 73 75 62 72 6f 75 74  69 6e 65 2c 20 74 68 65  | subroutine, the|
00004f80  20 63 6f 6d 6d 61 6e 64  20 73 68 6f 75 6c 64 20  | command should |
00004f90  62 65 20 6d 6f 64 69 66  69 65 64 20 74 6f 20 27  |be modified to '|
00004fa0  4d 4f 56 53 20 50 43 2c  52 31 34 27 2e 0a 23 77  |MOVS PC,R14'..#w|
00004fb0  72 61 70 20 6f 6e 00 00  44 41 54 41 fd 01 00 00  |rap on..DATA....|
00004fc0  4c 44 52 3a 20 4c 6f 61  64 20 74 6f 20 52 65 67  |LDR: Load to Reg|
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00004fe0  64 20 77 69 6d 70 20 31  0a 23 77 72 61 70 20 6f  |d wimp 1.#wrap o|
00004ff0  66 66 0a 4f 70 65 72 61  74 69 6f 6e 3a 20 44 61  |ff.Operation: Da|
00005000  74 61 20 74 72 61 6e 73  66 65 72 20 66 72 6f 6d  |ta transfer from|
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00005040  74 72 75 63 74 69 6f 6e  20 69 73 20 75 73 65 64  |truction is used|
00005050  20 74 6f 20 74 72 61 6e  73 66 65 72 20 64 61 74  | to transfer dat|
00005060  61 20 66 72 6f 6d 20 6d  65 6d 6f 72 79 20 69 6e  |a from memory in|
00005070  74 6f 20 74 68 65 20 72  65 67 69 73 74 65 72 73  |to the registers|
00005080  2e 20 41 20 73 79 73 74  65 6d 20 6f 66 20 69 6e  |. A system of in|
00005090  64 69 72 65 63 74 20 61  64 64 72 65 73 73 69 6e  |direct addressin|
000050a0  67 20 69 73 20 75 73 65  64 20 74 6f 20 73 70 65  |g is used to spe|
000050b0  63 69 66 79 20 74 68 65  20 73 6f 75 72 63 65 20  |cify the source |
000050c0  6c 6f 63 61 74 69 6f 6e  20 61 64 64 72 65 73 73  |location address|
000050d0  20 2d 20 74 68 65 20 61  64 64 72 65 73 73 20 74  | - the address t|
000050e0  6f 20 62 65 20 6c 6f 6f  6b 65 64 20 75 70 20 69  |o be looked up i|
000050f0  73 20 68 65 6c 64 20 69  6e 20 61 20 72 65 67 69  |s held in a regi|
00005100  73 74 65 72 2e 0a 54 68  65 72 65 20 61 72 65 20  |ster..There are |
00005110  74 77 6f 20 66 6f 72 6d  73 20 6f 66 20 69 6e 64  |two forms of ind|
00005120  69 72 65 63 74 20 61 64  64 72 65 73 73 69 6e 67  |irect addressing|
00005130  3a 20 3c 50 72 65 2d 69  6e 64 65 78 65 64 3d 3e  |: <Pre-indexed=>|
00005140  50 72 65 3e 20 61 6e 64  20 3c 50 6f 73 74 2d 69  |Pre> and <Post-i|
00005150  6e 64 65 78 65 64 3d 3e  50 6f 73 74 3e 2e 20 49  |ndexed=>Post>. I|
00005160  6e 20 61 64 64 69 74 69  6f 6e 20 74 6f 20 74 68  |n addition to th|
00005170  65 73 65 20 74 77 6f 20  66 6f 72 6d 73 2c 20 61  |ese two forms, a|
00005180  20 3c 50 43 20 72 65 6c  61 74 69 76 65 3d 3e 50  | <PC relative=>P|
00005190  43 5f 72 65 6c 3e 20 61  64 64 72 65 73 73 20 63  |C_rel> address c|
000051a0  61 6e 20 61 6c 73 6f 20  62 65 20 73 70 65 63 69  |an also be speci|
000051b0  66 69 65 64 2e 00 00 00  44 41 54 41 05 02 00 00  |fied....DATA....|
000051c0  53 54 52 3a 20 53 74 6f  72 65 20 66 72 6f 6d 20  |STR: Store from |
000051d0  52 65 67 69 73 74 65 72  0a 23 62 61 63 6b 67 72  |Register.#backgr|
000051e0  6f 75 6e 64 20 77 69 6d  70 20 31 0a 23 77 72 61  |ound wimp 1.#wra|
000051f0  70 20 6f 66 66 0a 4f 70  65 72 61 74 69 6f 6e 3a  |p off.Operation:|
00005200  20 44 61 74 61 20 74 72  61 6e 73 66 65 72 20 66  | Data transfer f|
00005210  72 6f 6d 20 74 68 65 20  72 65 67 69 73 74 65 72  |rom the register|
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00005230  70 20 6f 6e 0a 23 6c 69  6e 65 0a 54 68 69 73 20  |p on.#line.This |
00005240  69 6e 73 74 72 75 63 74  69 6f 6e 20 69 73 20 75  |instruction is u|
00005250  73 65 64 20 74 6f 20 74  72 61 6e 73 66 65 72 20  |sed to transfer |
00005260  64 61 74 61 20 66 72 6f  6d 20 74 68 65 20 72 65  |data from the re|
00005270  67 69 73 74 65 72 73 20  69 6e 74 6f 20 6d 65 6d  |gisters into mem|
00005280  6f 72 79 2e 20 41 20 73  79 73 74 65 6d 20 6f 66  |ory. A system of|
00005290  20 69 6e 64 69 72 65 63  74 20 61 64 64 72 65 73  | indirect addres|
000052a0  73 69 6e 67 20 69 73 20  75 73 65 64 20 74 6f 20  |sing is used to |
000052b0  73 70 65 63 69 66 79 20  74 68 65 20 64 65 73 74  |specify the dest|
000052c0  69 6e 61 74 69 6f 6e 20  6c 6f 63 61 74 69 6f 6e  |ination location|
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000052f0  6b 65 64 20 75 70 20 69  73 20 68 65 6c 64 20 69  |ked up is held i|
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00005310  65 72 65 20 61 72 65 20  74 77 6f 20 66 6f 72 6d  |ere are two form|
00005320  73 20 6f 66 20 69 6e 64  69 72 65 63 74 20 61 64  |s of indirect ad|
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00005340  6e 64 65 78 65 64 3d 3e  50 72 65 3e 20 61 6e 64  |ndexed=>Pre> and|
00005350  20 3c 50 6f 73 74 2d 69  6e 64 65 78 65 64 3d 3e  | <Post-indexed=>|
00005360  50 6f 73 74 3e 2e 20 49  6e 20 61 64 64 69 74 69  |Post>. In additi|
00005370  6f 6e 20 74 6f 20 74 68  65 73 65 20 74 77 6f 20  |on to these two |
00005380  66 6f 72 6d 73 2c 20 61  20 3c 50 43 20 72 65 6c  |forms, a <PC rel|
00005390  61 74 69 76 65 3d 3e 50  43 5f 72 65 6c 3e 20 61  |ative=>PC_rel> a|
000053a0  64 64 72 65 73 73 20 63  61 6e 20 61 6c 73 6f 20  |ddress can also |
000053b0  62 65 20 73 70 65 63 69  66 69 65 64 2e 00 00 00  |be specified....|
000053c0  44 41 54 41 36 01 00 00  42 79 74 65 20 61 64 64  |DATA6...Byte add|
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000053e0  75 6e 64 20 77 69 6d 70  20 31 0a 42 79 20 64 65  |und wimp 1.By de|
000053f0  66 61 75 6c 74 2c 20 3c  4c 44 52 3e 20 61 6e 64  |fault, <LDR> and|
00005400  20 3c 53 54 52 3e 20 61  63 63 65 73 73 20 63 6f  | <STR> access co|
00005410  6d 70 6c 65 74 65 20 77  6f 72 64 73 20 6f 66 20  |mplete words of |
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00005430  65 73 29 2e 20 48 6f 77  65 76 65 72 2c 20 74 68  |es). However, th|
00005440  65 79 20 63 61 6e 20 62  65 20 6d 61 64 65 20 74  |ey can be made t|
00005450  6f 20 61 63 63 65 73 73  20 73 69 6e 67 6c 65 20  |o access single |
00005460  62 79 74 65 73 20 75 73  69 6e 67 20 74 68 65 20  |bytes using the |
00005470  27 42 27 20 73 75 66 66  69 78 2e 0a 23 6c 69 6e  |'B' suffix..#lin|
00005480  65 0a 45 78 61 6d 70 6c  65 73 3a 0a 23 77 72 61  |e.Examples:.#wra|
00005490  70 20 6f 66 66 0a 23 69  6e 64 65 6e 74 20 32 0a  |p off.#indent 2.|
000054a0  4c 44 52 42 09 52 30 2c  5b 52 32 2c 52 34 5d 0a  |LDRB.R0,[R2,R4].|
000054b0  53 54 52 42 09 52 30 2c  5b 52 35 2c 23 34 5d 0a  |STRB.R0,[R5,#4].|
000054c0  4c 44 52 42 09 52 30 2c  5b 52 36 2c 52 35 2c 4c  |LDRB.R0,[R6,R5,L|
000054d0  53 52 23 36 5d 21 0a 4c  44 52 4e 45 42 09 52 30  |SR#6]!.LDRNEB.R0|
000054e0  2c 5b 52 31 5d 2c 52 33  0a 4c 44 52 42 09 52 30  |,[R1],R3.LDRB.R0|
000054f0  2c 74 61 62 6c 65 00 00  44 41 54 41 c3 02 00 00  |,table..DATA....|
00005500  50 43 20 72 65 6c 61 74  69 76 65 20 61 64 64 72  |PC relative addr|
00005510  65 73 73 69 6e 67 0a 23  62 61 63 6b 67 72 6f 75  |essing.#backgrou|
00005520  6e 64 20 77 69 6d 70 20  31 0a 23 77 72 61 70 20  |nd wimp 1.#wrap |
00005530  6f 66 66 0a 53 79 6e 74  61 78 3a 20 4c 44 52 20  |off.Syntax: LDR |
00005540  28 6f 72 20 53 54 52 29  20 5c 3c 64 65 73 74 69  |(or STR) \<desti|
00005550  6e 61 74 69 6f 6e 5c 3e  2c 61 64 64 72 65 73 73  |nation\>,address|
00005560  0a 23 77 72 61 70 20 6e  6f 6a 6f 69 6e 0a 23 6c  |.#wrap nojoin.#l|
00005570  69 6e 65 0a 50 43 20 72  65 6c 61 74 69 76 65 20  |ine.PC relative |
00005580  61 64 64 72 65 73 73 69  6e 67 20 69 73 20 61 20  |addressing is a |
00005590  70 73 65 75 64 6f 2d 61  64 64 72 65 73 73 69 6e  |pseudo-addressin|
000055a0  67 20 6d 6f 64 65 20 61  73 20 69 74 20 69 73 20  |g mode as it is |
000055b0  6e 6f 74 20 61 20 64 69  73 74 69 6e 63 74 20 61  |not a distinct a|
000055c0  64 64 72 65 73 73 69 6e  67 20 6d 6f 64 65 20 73  |ddressing mode s|
000055d0  75 70 70 6f 72 74 65 64  20 62 79 20 74 68 65 20  |upported by the |
000055e0  41 52 4d 2e 20 49 6e 73  74 65 61 64 2c 20 73 75  |ARM. Instead, su|
000055f0  63 68 20 69 6e 73 74 72  75 63 74 69 6f 6e 73 20  |ch instructions |
00005600  61 72 65 20 63 6f 6e 76  65 72 74 65 64 20 69 6e  |are converted in|
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00005620  65 20 70 72 65 2d 69 6e  64 65 78 65 64 20 69 6e  |e pre-indexed in|
00005630  73 74 72 75 63 74 69 6f  6e 20 62 79 20 74 68 65  |struction by the|
00005640  20 61 73 73 65 6d 62 6c  65 72 2e 0a 54 68 65 20  | assembler..The |
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00005670  6d 62 65 72 2c 20 6f 72  20 61 6e 20 61 73 73 65  |mber, or an asse|
00005680  6d 62 6c 65 72 20 6c 61  62 65 6c 2e 0a 23 6c 69  |mbler label..#li|
00005690  6e 65 0a 45 78 61 6d 70  6c 65 73 3a 0a 23 77 72  |ne.Examples:.#wr|
000056a0  61 70 20 6f 66 66 0a 23  69 6e 64 65 6e 74 20 32  |ap off.#indent 2|
000056b0  0a 4c 44 52 20 52 30 2c  26 31 30 30 30 09 4c 6f  |.LDR R0,&1000.Lo|
000056c0  61 64 20 77 6f 72 64 20  6f 66 20 6d 65 6d 6f 72  |ad word of memor|
000056d0  79 20 66 72 6f 6d 20 6c  6f 63 61 74 69 6f 6e 20  |y from location |
000056e0  26 31 30 30 30 20 69 6e  74 6f 20 52 30 0a 53 54  |&1000 into R0.ST|
000056f0  52 20 52 30 2c 74 61 62  6c 65 09 53 74 6f 72 65  |R R0,table.Store|
00005700  20 52 30 20 74 6f 20 77  6f 72 64 20 6f 66 20 6d  | R0 to word of m|
00005710  65 6d 6f 72 79 20 73 70  65 63 69 66 69 65 64 20  |emory specified |
00005720  62 79 20 27 74 61 62 6c  65 27 0a 23 69 6e 64 65  |by 'table'.#inde|
00005730  6e 74 0a 23 77 72 61 70  20 6f 6e 0a 23 6c 69 6e  |nt.#wrap on.#lin|
00005740  65 0a 49 74 20 69 73 20  69 6d 70 6f 72 74 61 6e  |e.It is importan|
00005750  74 20 74 6f 20 72 65 6d  65 6d 62 65 72 20 74 68  |t to remember th|
00005760  61 74 20 74 68 65 20 72  61 6e 67 65 20 6f 66 20  |at the range of |
00005770  74 68 65 20 6f 66 66 73  65 74 2c 20 61 73 20 69  |the offset, as i|
00005780  6e 20 3c 70 72 65 2d 69  6e 64 65 78 65 64 20 61  |n <pre-indexed a|
00005790  64 64 72 65 73 73 69 6e  67 3d 3e 50 72 65 3e 2c  |ddressing=>Pre>,|
000057a0  20 69 73 20 62 65 74 77  65 65 6e 20 2d 34 30 39  | is between -409|
000057b0  36 20 61 6e 64 20 34 30  39 36 2e 00 44 41 54 41  |6 and 4096..DATA|
000057c0  63 03 00 00 50 6f 73 74  2d 69 6e 64 65 78 65 64  |c...Post-indexed|
000057d0  20 61 64 64 72 65 73 73  69 6e 67 0a 23 62 61 63  | addressing.#bac|
000057e0  6b 67 72 6f 75 6e 64 20  77 69 6d 70 20 31 0a 23  |kground wimp 1.#|
000057f0  77 72 61 70 20 6f 66 66  0a 53 79 6e 74 61 78 3a  |wrap off.Syntax:|
00005800  20 4c 44 52 20 28 6f 72  20 53 54 52 29 20 5c 3c  | LDR (or STR) \<|
00005810  64 65 73 74 69 6e 61 74  69 6f 6e 5c 3e 2c 20 5b  |destination\>, [|
00005820  5c 3c 62 61 73 65 5c 3e  5d 2c 5c 3c 6f 66 66 73  |\<base\>],\<offs|
00005830  65 74 5c 3e 0a 23 77 72  61 70 20 6f 6e 0a 23 6c  |et\>.#wrap on.#l|
00005840  69 6e 65 0a 54 68 69 73  20 66 6f 72 6d 20 6f 66  |ine.This form of|
00005850  20 61 64 64 72 65 73 73  69 6e 67 20 69 73 20 76  | addressing is v|
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00005870  70 72 65 2d 69 6e 64 65  78 65 64 20 61 64 64 72  |pre-indexed addr|
00005880  65 73 73 69 6e 67 3d 3e  50 72 65 3e 2e 20 49 6e  |essing=>Pre>. In|
00005890  20 74 68 69 73 20 63 61  73 65 2c 20 68 6f 77 65  | this case, howe|
000058a0  76 65 72 2c 20 74 68 65  20 6f 66 66 73 65 74 20  |ver, the offset |
000058b0  66 69 65 6c 64 20 69 73  20 2a 6e 6f 74 2a 20 6f  |field is *not* o|
000058c0  70 74 69 6f 6e 61 6c 2e  0a 23 6c 69 6e 65 0a 45  |ptional..#line.E|
000058d0  78 61 6d 70 6c 65 73 3a  0a 23 77 72 61 70 20 6f  |xamples:.#wrap o|
000058e0  66 66 0a 23 69 6e 64 65  6e 74 20 32 0a 4c 44 52  |ff.#indent 2.LDR|
000058f0  20 52 31 2c 5b 52 30 5d  2c 52 37 09 09 4c 6f 61  | R1,[R0],R7..Loa|
00005900  64 20 52 31 20 66 72 6f  6d 20 61 64 64 72 65 73  |d R1 from addres|
00005910  73 20 52 30 09 3a 20 52  30 3d 52 30 2b 52 37 0a  |s R0.: R0=R0+R7.|
00005920  53 54 52 20 52 36 2c 5b  52 37 5d 2c 23 34 09 09  |STR R6,[R7],#4..|
00005930  53 74 6f 72 65 20 52 36  20 61 74 20 61 64 64 72  |Store R6 at addr|
00005940  65 73 73 20 52 37 09 3a  20 52 37 3d 52 37 2b 34  |ess R7.: R7=R7+4|
00005950  0a 4c 44 52 20 52 38 2c  5b 52 32 5d 2c 52 35 2c  |.LDR R8,[R2],R5,|
00005960  4c 53 4c 23 34 09 4c 6f  61 64 20 52 38 20 66 72  |LSL#4.Load R8 fr|
00005970  6f 6d 20 61 64 64 72 65  73 73 20 52 32 09 3a 20  |om address R2.: |
00005980  52 32 3d 52 32 2b 52 35  2a 31 36 0a 53 54 52 20  |R2=R2+R5*16.STR |
00005990  52 30 2c 5b 52 30 5d 2c  23 32 30 09 09 53 74 6f  |R0,[R0],#20..Sto|
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00005ae0  74 68 61 74 20 77 72 69  74 65 20 62 61 63 6b 20  |that write back |
00005af0  61 6c 77 61 79 73 20 6f  63 63 75 72 73 2c 20 73  |always occurs, s|
00005b00  6f 20 77 65 20 64 6f 20  6e 6f 74 20 6e 65 65 64  |o we do not need|
00005b10  20 74 6f 20 73 70 65 63  69 66 79 20 69 74 2e 00  | to specify it..|
00005b20  44 41 54 41 21 03 00 00  50 72 65 2d 69 6e 64 65  |DATA!...Pre-inde|
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00005b40  62 61 63 6b 67 72 6f 75  6e 64 20 77 69 6d 70 20  |background wimp |
00005b50  31 0a 23 77 72 61 70 20  6f 66 66 0a 53 79 6e 74  |1.#wrap off.Synt|
00005b60  61 78 3a 20 4c 44 52 20  28 6f 72 20 53 54 52 29  |ax: LDR (or STR)|
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00005cb0  72 65 71 75 69 72 65 64  20 61 64 64 72 65 73 73  |required address|
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00005d40  6e 64 65 6e 74 20 32 0a  4c 44 52 20 52 30 2c 5b  |ndent 2.LDR R0,[|
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00005d90  20 52 31 20 2b 20 52 32  0a 4c 44 52 20 52 30 2c  | R1 + R2.LDR R0,|
00005da0  5b 52 31 2c 23 2d 34 5d  09 09 4c 6f 61 64 20 52  |[R1,#-4]..Load R|
00005db0  30 20 66 72 6f 6d 20 61  64 64 72 65 73 73 20 52  |0 from address R|
00005dc0  31 20 2d 20 34 0a 53 54  52 20 52 30 2c 5b 52 31  |1 - 4.STR R0,[R1|
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00005de0  20 52 30 20 61 74 20 61  64 64 72 65 73 73 20 52  | R0 at address R|
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00005f00  73 65 66 75 6c 20 74 6f  20 72 65 74 61 69 6e 20  |seful to retain |
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00005f20  6c 61 74 65 64 20 61 64  64 72 65 73 73 20 66 6f  |lated address fo|
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00005f40  20 70 72 65 2d 69 6e 64  65 78 65 64 20 61 64 64  | pre-indexed add|
00005f50  72 65 73 73 69 6e 67 2c  20 74 68 69 73 20 69 73  |ressing, this is|
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00005fd0  6d 70 6c 65 73 3a 0a 23  69 6e 64 65 6e 74 20 32  |mples:.#indent 2|
00005fe0  0a 4c 44 52 20 52 30 2c  5b 52 31 2c 52 32 5d 21  |.LDR R0,[R1,R2]!|
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00008320  0a 2a 4e 42 2a 3a 20 54  68 65 20 75 73 65 20 6f  |.*NB*: The use o|
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000084f0  41 09 46 75 6c 6c 2c 20  61 73 63 65 6e 64 69 6e  |A.Full, ascendin|
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0000ab30  20 53 31 20 53 30 00 00                           | S1 S0..|
0000ab38

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