Home » CEEFAX disks » telesoftware14.adl » 12-03-89/Counter
12-03-89/Counter
This website contains an archive of files for the Acorn Electron, BBC Micro, Acorn Archimedes, Commodore 16 and Commodore 64 computers, which Dominic Ford has rescued from his private collection of floppy disks and cassettes.
Some of these files were originally commercial releases in the 1980s and 1990s, but they are now widely available online. I assume that copyright over them is no longer being asserted. If you own the copyright and would like files to be removed, please contact me.
| Tape/disk: | Home » CEEFAX disks » telesoftware14.adl |
| Filename: | 12-03-89/Counter |
| Read OK: | ✔ |
| File size: | 0C9E bytes |
| Load address: | FFFF1900 |
| Exec address: | FFFF8023 |
File contents
10REM> COUNTER
20MODE7
30DIM mcode &200 :REM: space for machine code
40PROCmcode :REM: assemble machine code
50ttx$=CHR$(141)+CHR$(132)+CHR$(157)+CHR$(131)+"TTX interrupt counter "+CHR$(156)
60PRINTTAB(5,3)ttx$
70PRINTTAB(5,4)ttx$
80INPUTTAB(9,8)"TV channel (1-4) = "answer$
90VDU23,1,0;0;0;0;
100channel?0=EVAL("&"+LEFT$(answer$,1))+&1B
110IF channel?0 < &1C THEN channel?0 = &1C
120IF channel?0 > &1F THEN channel?0 = &1F
130TIME=0
140CALL mcode
150time=TIME/100
160count=EVAL(STR$~(counter!0))
170at%=@%
180@%=&20205
190PRINTTAB(6,16);count/time;" interrupts per second"
200@%=at%
210VDU31,0,22,23,1,1;0;0;0;
220END
230DEFPROCmcode
240channel=&70 :REM: TV channel
250savereg=&FC :REM: interrupt accumulator save register
260escape=&FF :REM: escape flag
270irq2v=&206 :REM: irq2 vector
280ttxcontrol=&FC10 :REM: TTX control register, write only
290ttxstatus=&FC10 :REM: TTX status register, read only
300rowreg=&FC11 :REM: TTX row register, write only
310datareg=&FC12 :REM: TTX data register, read & write
320statclr=&FC13 :REM: TTX clear status register, read & write
330oswrch=&FFEE
340osbyte=&FFF4
350FOR pass=0 TO 2 STEP 2
360P%=mcode
370[OPT pass
380LDX irq2v \ load secondary interrupt vector
390LDY irq2v+1
400STX oldirq2v \ save secondary interrupt vector
410STY oldirq2v+1
420LDX #interrupt MOD 256 \ install new interrupt routine
430LDY #interrupt DIV 256
440SEI \ disable interrupts when altering vector
450STX irq2v
460STY irq2v+1
470CLI \ re-enable interrupts
480LDA channel \ load (channel number + #&1C)
490STA ttxcontrol \ enable TTX
500.mainloop
510LDA #&1F \ decimal 31
520JSR oswrch
530LDA #&0F \ decimal 15
540JSR oswrch
550LDA #&0C \ decimal 12
560JSR oswrch \ VDU 31,14,14
570LDA counter+3
580JSR printbcd \ print 4 byte counter in hex.
590LDA counter+2
600JSR printbcd
610LDA counter+1
620JSR printbcd
630LDA counter
640JSR printbcd
650LDA escape \ poll escape flag
660BPL mainloop \ branch if escape not pressed
670LDA #&7E
680JSR osbyte \ acknowledge escape
690LDA #&00
700STA ttxcontrol \ disable TTX
710LDX oldirq2v \ load original vector
720LDY oldirq2v+1
730SEI \ disable interrupts when altering vector
740STX irq2v \ restore original vector
750STY irq2v+1
760CLI \ re-enable interrupts
770RTS \ return to BASIC
780.interrupt
790BIT ttxstatus \ poll TTX hardware
800BMI ttxinter \ branch if TTX interrupt
810JMP (oldirq2v) \ not TTX interrupt
820.ttxinter
830LDA savereg \ interrupt accumulator save register
840PHA \ push interrupt accumulator save register
850TXA
860PHA \ push X
870TYA
880PHA \ push Y
890SED
900CLC
910LDA #&01
920ADC counter \ add 1 for every TTX interrupt
930STA counter
940LDA #&00
950ADC counter+1
960STA counter+1
970LDA #&00
980ADC counter+2
990STA counter+2
1000LDA #&00
1010ADC counter+3
1020STA counter+3
1030LDA #&00
1040LDY #&0F \ clear 16 rows in adaptor
1050.clearloop
1060STY rowreg
1070STA datareg
1080DEY
1090BPL clearloop
1100STA statclr \ clear status flags before returning
1110PLA
1120TAY \ restore Y
1130PLA
1140TAX \ restore X
1150PLA
1160STA savereg \ restore interrupt accumulator save register
1170RTI \ return from interrupt
1180.printbcd
1190PHA
1200LSR A
1210LSR A
1220LSR A
1230LSR A
1240JSR nybble
1250PLA
1260.nybble
1270AND #&0F \ decimal 15
1280SED
1290CLC
1300ADC #&90 \ decimal 144
1310ADC #&40 \ decimal 64
1320CLD
1330JMP oswrch
1340.counter
1350EQUD &00
1360.oldirq2v
1370EQUW &00
1380]
1390NEXT
1400ENDPROC
�> COUNTER
�7
+� mcode &200 :�: space for machine code
($�mcode :�: assemble machine code
2Ettx$=�(141)+�(132)+�(157)+�(131)+"TTX interrupt counter "+�(156)
<�5,3)ttx$
F�5,4)ttx$
P&�9,8)"TV channel (1-4) = "answer$
Z�23,1,0;0;0;0;
d$channel?0=�("&"+�answer$,1))+&1B
n'� channel?0 < &1C � channel?0 = &1C
x'� channel?0 > &1F � channel?0 = &1F
��=0
� � mcode
�time=�/100
�count=�(�~(counter!0))
�
at%=@%
�
@%=&20205
�/�6,16);count/time;" interrupts per second"
�
@%=at%
��31,0,22,23,1,1;0;0;0;
��
� ��mcode
� channel=&70 :�: TV channel
�7savereg=&FC :�: interrupt accumulator save register
escape=&FF :�: escape flag
irq2v=&206 :�: irq2 vector
9ttxcontrol=&FC10 :�: TTX control register, write only
"6ttxstatus=&FC10 :�: TTX status register, read only
,1rowreg=&FC11 :�: TTX row register, write only
65datareg=&FC12 :�: TTX data register, read & write
@=statclr=&FC13 :�: TTX clear status register, read & write
Joswrch=&FFEE
Tosbyte=&FFF4
^� pass=0 � 2 � 2
h P%=mcode
r
[OPT pass
|/LDX irq2v \ load secondary interrupt vector
�LDY irq2v+1
�2STX oldirq2v \ save secondary interrupt vector
�STY oldirq2v+1
�8LDX #interrupt � 256 \ install new interrupt routine
�LDY #interrupt � 256
�1SEI \ disable interrupts when altering vector
�
STX irq2v
�STY irq2v+1
� CLI \ re-enable interrupts
�.LDA channel \ load (channel number + #&1C)
� STA ttxcontrol \ enable TTX
�
.mainloop
�LDA #&1F \ decimal 31
JSR oswrch
LDA #&0F \ decimal 15
JSR oswrch
&LDA #&0C \ decimal 12
0JSR oswrch \ � 31,14,14
:LDA counter+3
D/JSR printbcd \ print 4 byte counter in hex.
NLDA counter+2
XJSR printbcd
bLDA counter+1
lJSR printbcd
vLDA counter
�JSR printbcd
�!LDA escape \ poll escape flag
�/BPL mainloop \ branch if escape not pressed
� LDA #&7E
�#JSR osbyte \ acknowledge escape
� LDA #&00
� STA ttxcontrol \ disable TTX
�'LDX oldirq2v \ load original vector
�LDY oldirq2v+1
�1SEI \ disable interrupts when altering vector
�'STX irq2v \ restore original vector
�STY irq2v+1
� CLI \ re-enable interrupts
RTS \ return to BASIC
.interrupt
%BIT ttxstatus \ poll TTX hardware
*BMI ttxinter \ branch if TTX interrupt
*&JMP (oldirq2v) \ not TTX interrupt
4
.ttxinter
>5LDA savereg \ interrupt accumulator save register
H2PHA \ push interrupt accumulator save register
RTXA
\PHA \ push X
fTYA
pPHA \ push Y
zSED
�CLC
� LDA #&01
�/ADC counter \ add 1 for every TTX interrupt
�STA counter
� LDA #&00
�ADC counter+1
�STA counter+1
� LDA #&00
�ADC counter+2
�STA counter+2
� LDA #&00
�ADC counter+3
�STA counter+3
LDA #&00
'LDY #&0F \ clear 16 rows in adaptor
.clearloop
$STY rowreg
.STA datareg
8DEY
BBPL clearloop
L5STA statclr \ clear status flags before returning
VPLA
`TAY \ restore Y
jPLA
tTAX \ restore X
~PLA
�=STA savereg \ restore interrupt accumulator save register
� RTI \ return from interrupt
�
.printbcd
�PHA
� LSR A
� LSR A
� LSR A
� LSR A
�JSR nybble
�PLA
� .nybble
�� #&0F \ decimal 15
SED
CLC
ADC #&90 \ decimal 144
ADC #&40 \ decimal 64
(CLD
2JMP oswrch
< .counter
F EQUD &00
P
.oldirq2v
Z EQUW &00
d]
n�
x�
� 00000000 0d 00 0a 0e f4 3e 20 43 4f 55 4e 54 45 52 0d 00 |.....> COUNTER..|
00000010 14 06 eb 37 0d 00 1e 2b de 20 6d 63 6f 64 65 20 |...7...+. mcode |
00000020 26 32 30 30 20 3a f4 3a 20 73 70 61 63 65 20 66 |&200 :.: space f|
00000030 6f 72 20 6d 61 63 68 69 6e 65 20 63 6f 64 65 0d |or machine code.|
00000040 00 28 24 f2 6d 63 6f 64 65 20 3a f4 3a 20 61 73 |.($.mcode :.: as|
00000050 73 65 6d 62 6c 65 20 6d 61 63 68 69 6e 65 20 63 |semble machine c|
00000060 6f 64 65 0d 00 32 45 74 74 78 24 3d bd 28 31 34 |ode..2Ettx$=.(14|
00000070 31 29 2b bd 28 31 33 32 29 2b bd 28 31 35 37 29 |1)+.(132)+.(157)|
00000080 2b bd 28 31 33 31 29 2b 22 54 54 58 20 69 6e 74 |+.(131)+"TTX int|
00000090 65 72 72 75 70 74 20 63 6f 75 6e 74 65 72 20 20 |errupt counter |
000000a0 22 2b bd 28 31 35 36 29 0d 00 3c 0e f1 8a 35 2c |"+.(156)..<...5,|
000000b0 33 29 74 74 78 24 0d 00 46 0e f1 8a 35 2c 34 29 |3)ttx$..F...5,4)|
000000c0 74 74 78 24 0d 00 50 26 e8 8a 39 2c 38 29 22 54 |ttx$..P&..9,8)"T|
000000d0 56 20 63 68 61 6e 6e 65 6c 20 28 31 2d 34 29 20 |V channel (1-4) |
000000e0 3d 20 22 61 6e 73 77 65 72 24 0d 00 5a 12 ef 32 |= "answer$..Z..2|
000000f0 33 2c 31 2c 30 3b 30 3b 30 3b 30 3b 0d 00 64 24 |3,1,0;0;0;0;..d$|
00000100 63 68 61 6e 6e 65 6c 3f 30 3d a0 28 22 26 22 2b |channel?0=.("&"+|
00000110 c0 61 6e 73 77 65 72 24 2c 31 29 29 2b 26 31 42 |.answer$,1))+&1B|
00000120 0d 00 6e 27 e7 20 63 68 61 6e 6e 65 6c 3f 30 20 |..n'. channel?0 |
00000130 3c 20 26 31 43 20 8c 20 63 68 61 6e 6e 65 6c 3f |< &1C . channel?|
00000140 30 20 3d 20 26 31 43 0d 00 78 27 e7 20 63 68 61 |0 = &1C..x'. cha|
00000150 6e 6e 65 6c 3f 30 20 3e 20 26 31 46 20 8c 20 63 |nnel?0 > &1F . c|
00000160 68 61 6e 6e 65 6c 3f 30 20 3d 20 26 31 46 0d 00 |hannel?0 = &1F..|
00000170 82 07 d1 3d 30 0d 00 8c 0b d6 20 6d 63 6f 64 65 |...=0..... mcode|
00000180 0d 00 96 0e 74 69 6d 65 3d 91 2f 31 30 30 0d 00 |....time=./100..|
00000190 a0 1a 63 6f 75 6e 74 3d a0 28 c3 7e 28 63 6f 75 |..count=.(.~(cou|
000001a0 6e 74 65 72 21 30 29 29 0d 00 aa 0a 61 74 25 3d |nter!0))....at%=|
000001b0 40 25 0d 00 b4 0d 40 25 3d 26 32 30 32 30 35 0d |@%....@%=&20205.|
000001c0 00 be 2f f1 8a 36 2c 31 36 29 3b 63 6f 75 6e 74 |../..6,16);count|
000001d0 2f 74 69 6d 65 3b 22 20 69 6e 74 65 72 72 75 70 |/time;" interrup|
000001e0 74 73 20 70 65 72 20 73 65 63 6f 6e 64 22 0d 00 |ts per second"..|
000001f0 c8 0a 40 25 3d 61 74 25 0d 00 d2 1a ef 33 31 2c |..@%=at%.....31,|
00000200 30 2c 32 32 2c 32 33 2c 31 2c 31 3b 30 3b 30 3b |0,22,23,1,1;0;0;|
00000210 30 3b 0d 00 dc 05 e0 0d 00 e6 0b dd f2 6d 63 6f |0;...........mco|
00000220 64 65 0d 00 f0 1e 63 68 61 6e 6e 65 6c 3d 26 37 |de....channel=&7|
00000230 30 20 3a f4 3a 20 54 56 20 63 68 61 6e 6e 65 6c |0 :.: TV channel|
00000240 0d 00 fa 37 73 61 76 65 72 65 67 3d 26 46 43 20 |...7savereg=&FC |
00000250 3a f4 3a 20 69 6e 74 65 72 72 75 70 74 20 61 63 |:.: interrupt ac|
00000260 63 75 6d 75 6c 61 74 6f 72 20 73 61 76 65 20 72 |cumulator save r|
00000270 65 67 69 73 74 65 72 0d 01 04 1e 65 73 63 61 70 |egister....escap|
00000280 65 3d 26 46 46 20 3a f4 3a 20 65 73 63 61 70 65 |e=&FF :.: escape|
00000290 20 66 6c 61 67 0d 01 0e 1e 69 72 71 32 76 3d 26 | flag....irq2v=&|
000002a0 32 30 36 20 3a f4 3a 20 69 72 71 32 20 76 65 63 |206 :.: irq2 vec|
000002b0 74 6f 72 0d 01 18 39 74 74 78 63 6f 6e 74 72 6f |tor...9ttxcontro|
000002c0 6c 3d 26 46 43 31 30 20 3a f4 3a 20 54 54 58 20 |l=&FC10 :.: TTX |
000002d0 63 6f 6e 74 72 6f 6c 20 72 65 67 69 73 74 65 72 |control register|
000002e0 2c 20 77 72 69 74 65 20 6f 6e 6c 79 0d 01 22 36 |, write only.."6|
000002f0 74 74 78 73 74 61 74 75 73 3d 26 46 43 31 30 20 |ttxstatus=&FC10 |
00000300 3a f4 3a 20 54 54 58 20 73 74 61 74 75 73 20 72 |:.: TTX status r|
00000310 65 67 69 73 74 65 72 2c 20 72 65 61 64 20 6f 6e |egister, read on|
00000320 6c 79 0d 01 2c 31 72 6f 77 72 65 67 3d 26 46 43 |ly..,1rowreg=&FC|
00000330 31 31 20 3a f4 3a 20 54 54 58 20 72 6f 77 20 72 |11 :.: TTX row r|
00000340 65 67 69 73 74 65 72 2c 20 77 72 69 74 65 20 6f |egister, write o|
00000350 6e 6c 79 0d 01 36 35 64 61 74 61 72 65 67 3d 26 |nly..65datareg=&|
00000360 46 43 31 32 20 3a f4 3a 20 54 54 58 20 64 61 74 |FC12 :.: TTX dat|
00000370 61 20 72 65 67 69 73 74 65 72 2c 20 72 65 61 64 |a register, read|
00000380 20 26 20 77 72 69 74 65 0d 01 40 3d 73 74 61 74 | & write..@=stat|
00000390 63 6c 72 3d 26 46 43 31 33 20 3a f4 3a 20 54 54 |clr=&FC13 :.: TT|
000003a0 58 20 63 6c 65 61 72 20 73 74 61 74 75 73 20 72 |X clear status r|
000003b0 65 67 69 73 74 65 72 2c 20 72 65 61 64 20 26 20 |egister, read & |
000003c0 77 72 69 74 65 0d 01 4a 10 6f 73 77 72 63 68 3d |write..J.oswrch=|
000003d0 26 46 46 45 45 0d 01 54 10 6f 73 62 79 74 65 3d |&FFEE..T.osbyte=|
000003e0 26 46 46 46 34 0d 01 5e 14 e3 20 70 61 73 73 3d |&FFF4..^.. pass=|
000003f0 30 20 b8 20 32 20 88 20 32 0d 01 68 0c 50 25 3d |0 . 2 . 2..h.P%=|
00000400 6d 63 6f 64 65 0d 01 72 0d 5b 4f 50 54 20 70 61 |mcode..r.[OPT pa|
00000410 73 73 0d 01 7c 2f 4c 44 58 20 69 72 71 32 76 20 |ss..|/LDX irq2v |
00000420 5c 20 6c 6f 61 64 20 73 65 63 6f 6e 64 61 72 79 |\ load secondary|
00000430 20 69 6e 74 65 72 72 75 70 74 20 76 65 63 74 6f | interrupt vecto|
00000440 72 0d 01 86 0f 4c 44 59 20 69 72 71 32 76 2b 31 |r....LDY irq2v+1|
00000450 0d 01 90 32 53 54 58 20 6f 6c 64 69 72 71 32 76 |...2STX oldirq2v|
00000460 20 5c 20 73 61 76 65 20 73 65 63 6f 6e 64 61 72 | \ save secondar|
00000470 79 20 69 6e 74 65 72 72 75 70 74 20 76 65 63 74 |y interrupt vect|
00000480 6f 72 0d 01 9a 12 53 54 59 20 6f 6c 64 69 72 71 |or....STY oldirq|
00000490 32 76 2b 31 0d 01 a4 38 4c 44 58 20 23 69 6e 74 |2v+1...8LDX #int|
000004a0 65 72 72 75 70 74 20 83 20 32 35 36 20 5c 20 69 |errupt . 256 \ i|
000004b0 6e 73 74 61 6c 6c 20 6e 65 77 20 69 6e 74 65 72 |nstall new inter|
000004c0 72 75 70 74 20 72 6f 75 74 69 6e 65 0d 01 ae 18 |rupt routine....|
000004d0 4c 44 59 20 23 69 6e 74 65 72 72 75 70 74 20 81 |LDY #interrupt .|
000004e0 20 32 35 36 0d 01 b8 31 53 45 49 20 5c 20 64 69 | 256...1SEI \ di|
000004f0 73 61 62 6c 65 20 69 6e 74 65 72 72 75 70 74 73 |sable interrupts|
00000500 20 77 68 65 6e 20 61 6c 74 65 72 69 6e 67 20 76 | when altering v|
00000510 65 63 74 6f 72 0d 01 c2 0d 53 54 58 20 69 72 71 |ector....STX irq|
00000520 32 76 0d 01 cc 0f 53 54 59 20 69 72 71 32 76 2b |2v....STY irq2v+|
00000530 31 0d 01 d6 1e 43 4c 49 20 5c 20 72 65 2d 65 6e |1....CLI \ re-en|
00000540 61 62 6c 65 20 69 6e 74 65 72 72 75 70 74 73 0d |able interrupts.|
00000550 01 e0 2e 4c 44 41 20 63 68 61 6e 6e 65 6c 20 5c |...LDA channel \|
00000560 20 6c 6f 61 64 20 28 63 68 61 6e 6e 65 6c 20 6e | load (channel n|
00000570 75 6d 62 65 72 20 2b 20 23 26 31 43 29 0d 01 ea |umber + #&1C)...|
00000580 1f 53 54 41 20 74 74 78 63 6f 6e 74 72 6f 6c 20 |.STA ttxcontrol |
00000590 5c 20 65 6e 61 62 6c 65 20 54 54 58 0d 01 f4 0d |\ enable TTX....|
000005a0 2e 6d 61 69 6e 6c 6f 6f 70 0d 01 fe 19 4c 44 41 |.mainloop....LDA|
000005b0 20 23 26 31 46 20 5c 20 64 65 63 69 6d 61 6c 20 | #&1F \ decimal |
000005c0 33 31 0d 02 08 0e 4a 53 52 20 6f 73 77 72 63 68 |31....JSR oswrch|
000005d0 0d 02 12 19 4c 44 41 20 23 26 30 46 20 5c 20 64 |....LDA #&0F \ d|
000005e0 65 63 69 6d 61 6c 20 31 35 0d 02 1c 0e 4a 53 52 |ecimal 15....JSR|
000005f0 20 6f 73 77 72 63 68 0d 02 26 19 4c 44 41 20 23 | oswrch..&.LDA #|
00000600 26 30 43 20 5c 20 64 65 63 69 6d 61 6c 20 31 32 |&0C \ decimal 12|
00000610 0d 02 30 1b 4a 53 52 20 6f 73 77 72 63 68 20 5c |..0.JSR oswrch \|
00000620 20 ef 20 33 31 2c 31 34 2c 31 34 0d 02 3a 11 4c | . 31,14,14..:.L|
00000630 44 41 20 63 6f 75 6e 74 65 72 2b 33 0d 02 44 2f |DA counter+3..D/|
00000640 4a 53 52 20 70 72 69 6e 74 62 63 64 20 5c 20 70 |JSR printbcd \ p|
00000650 72 69 6e 74 20 34 20 62 79 74 65 20 63 6f 75 6e |rint 4 byte coun|
00000660 74 65 72 20 69 6e 20 68 65 78 2e 0d 02 4e 11 4c |ter in hex...N.L|
00000670 44 41 20 63 6f 75 6e 74 65 72 2b 32 0d 02 58 10 |DA counter+2..X.|
00000680 4a 53 52 20 70 72 69 6e 74 62 63 64 0d 02 62 11 |JSR printbcd..b.|
00000690 4c 44 41 20 63 6f 75 6e 74 65 72 2b 31 0d 02 6c |LDA counter+1..l|
000006a0 10 4a 53 52 20 70 72 69 6e 74 62 63 64 0d 02 76 |.JSR printbcd..v|
000006b0 0f 4c 44 41 20 63 6f 75 6e 74 65 72 0d 02 80 10 |.LDA counter....|
000006c0 4a 53 52 20 70 72 69 6e 74 62 63 64 0d 02 8a 21 |JSR printbcd...!|
000006d0 4c 44 41 20 65 73 63 61 70 65 20 5c 20 70 6f 6c |LDA escape \ pol|
000006e0 6c 20 65 73 63 61 70 65 20 66 6c 61 67 0d 02 94 |l escape flag...|
000006f0 2f 42 50 4c 20 6d 61 69 6e 6c 6f 6f 70 20 5c 20 |/BPL mainloop \ |
00000700 62 72 61 6e 63 68 20 69 66 20 65 73 63 61 70 65 |branch if escape|
00000710 20 6e 6f 74 20 70 72 65 73 73 65 64 0d 02 9e 0c | not pressed....|
00000720 4c 44 41 20 23 26 37 45 0d 02 a8 23 4a 53 52 20 |LDA #&7E...#JSR |
00000730 6f 73 62 79 74 65 20 5c 20 61 63 6b 6e 6f 77 6c |osbyte \ acknowl|
00000740 65 64 67 65 20 65 73 63 61 70 65 0d 02 b2 0c 4c |edge escape....L|
00000750 44 41 20 23 26 30 30 0d 02 bc 20 53 54 41 20 74 |DA #&00... STA t|
00000760 74 78 63 6f 6e 74 72 6f 6c 20 5c 20 64 69 73 61 |txcontrol \ disa|
00000770 62 6c 65 20 54 54 58 0d 02 c6 27 4c 44 58 20 6f |ble TTX...'LDX o|
00000780 6c 64 69 72 71 32 76 20 5c 20 6c 6f 61 64 20 6f |ldirq2v \ load o|
00000790 72 69 67 69 6e 61 6c 20 76 65 63 74 6f 72 0d 02 |riginal vector..|
000007a0 d0 12 4c 44 59 20 6f 6c 64 69 72 71 32 76 2b 31 |..LDY oldirq2v+1|
000007b0 0d 02 da 31 53 45 49 20 5c 20 64 69 73 61 62 6c |...1SEI \ disabl|
000007c0 65 20 69 6e 74 65 72 72 75 70 74 73 20 77 68 65 |e interrupts whe|
000007d0 6e 20 61 6c 74 65 72 69 6e 67 20 76 65 63 74 6f |n altering vecto|
000007e0 72 0d 02 e4 27 53 54 58 20 69 72 71 32 76 20 5c |r...'STX irq2v \|
000007f0 20 72 65 73 74 6f 72 65 20 6f 72 69 67 69 6e 61 | restore origina|
00000800 6c 20 76 65 63 74 6f 72 0d 02 ee 0f 53 54 59 20 |l vector....STY |
00000810 69 72 71 32 76 2b 31 0d 02 f8 1e 43 4c 49 20 5c |irq2v+1....CLI \|
00000820 20 72 65 2d 65 6e 61 62 6c 65 20 69 6e 74 65 72 | re-enable inter|
00000830 72 75 70 74 73 0d 03 02 19 52 54 53 20 5c 20 72 |rupts....RTS \ r|
00000840 65 74 75 72 6e 20 74 6f 20 42 41 53 49 43 0d 03 |eturn to BASIC..|
00000850 0c 0e 2e 69 6e 74 65 72 72 75 70 74 0d 03 16 25 |...interrupt...%|
00000860 42 49 54 20 74 74 78 73 74 61 74 75 73 20 5c 20 |BIT ttxstatus \ |
00000870 70 6f 6c 6c 20 54 54 58 20 68 61 72 64 77 61 72 |poll TTX hardwar|
00000880 65 0d 03 20 2a 42 4d 49 20 74 74 78 69 6e 74 65 |e.. *BMI ttxinte|
00000890 72 20 5c 20 62 72 61 6e 63 68 20 69 66 20 54 54 |r \ branch if TT|
000008a0 58 20 69 6e 74 65 72 72 75 70 74 0d 03 2a 26 4a |X interrupt..*&J|
000008b0 4d 50 20 28 6f 6c 64 69 72 71 32 76 29 20 5c 20 |MP (oldirq2v) \ |
000008c0 6e 6f 74 20 54 54 58 20 69 6e 74 65 72 72 75 70 |not TTX interrup|
000008d0 74 0d 03 34 0d 2e 74 74 78 69 6e 74 65 72 0d 03 |t..4..ttxinter..|
000008e0 3e 35 4c 44 41 20 73 61 76 65 72 65 67 20 5c 20 |>5LDA savereg \ |
000008f0 69 6e 74 65 72 72 75 70 74 20 61 63 63 75 6d 75 |interrupt accumu|
00000900 6c 61 74 6f 72 20 73 61 76 65 20 72 65 67 69 73 |lator save regis|
00000910 74 65 72 0d 03 48 32 50 48 41 20 5c 20 70 75 73 |ter..H2PHA \ pus|
00000920 68 20 69 6e 74 65 72 72 75 70 74 20 61 63 63 75 |h interrupt accu|
00000930 6d 75 6c 61 74 6f 72 20 73 61 76 65 20 72 65 67 |mulator save reg|
00000940 69 73 74 65 72 0d 03 52 07 54 58 41 0d 03 5c 10 |ister..R.TXA..\.|
00000950 50 48 41 20 5c 20 70 75 73 68 20 58 0d 03 66 07 |PHA \ push X..f.|
00000960 54 59 41 0d 03 70 10 50 48 41 20 5c 20 70 75 73 |TYA..p.PHA \ pus|
00000970 68 20 59 0d 03 7a 07 53 45 44 0d 03 84 07 43 4c |h Y..z.SED....CL|
00000980 43 0d 03 8e 0c 4c 44 41 20 23 26 30 31 0d 03 98 |C....LDA #&01...|
00000990 2f 41 44 43 20 63 6f 75 6e 74 65 72 20 5c 20 61 |/ADC counter \ a|
000009a0 64 64 20 31 20 66 6f 72 20 65 76 65 72 79 20 54 |dd 1 for every T|
000009b0 54 58 20 69 6e 74 65 72 72 75 70 74 0d 03 a2 0f |TX interrupt....|
000009c0 53 54 41 20 63 6f 75 6e 74 65 72 0d 03 ac 0c 4c |STA counter....L|
000009d0 44 41 20 23 26 30 30 0d 03 b6 11 41 44 43 20 63 |DA #&00....ADC c|
000009e0 6f 75 6e 74 65 72 2b 31 0d 03 c0 11 53 54 41 20 |ounter+1....STA |
000009f0 63 6f 75 6e 74 65 72 2b 31 0d 03 ca 0c 4c 44 41 |counter+1....LDA|
00000a00 20 23 26 30 30 0d 03 d4 11 41 44 43 20 63 6f 75 | #&00....ADC cou|
00000a10 6e 74 65 72 2b 32 0d 03 de 11 53 54 41 20 63 6f |nter+2....STA co|
00000a20 75 6e 74 65 72 2b 32 0d 03 e8 0c 4c 44 41 20 23 |unter+2....LDA #|
00000a30 26 30 30 0d 03 f2 11 41 44 43 20 63 6f 75 6e 74 |&00....ADC count|
00000a40 65 72 2b 33 0d 03 fc 11 53 54 41 20 63 6f 75 6e |er+3....STA coun|
00000a50 74 65 72 2b 33 0d 04 06 0c 4c 44 41 20 23 26 30 |ter+3....LDA #&0|
00000a60 30 0d 04 10 27 4c 44 59 20 23 26 30 46 20 5c 20 |0...'LDY #&0F \ |
00000a70 63 6c 65 61 72 20 31 36 20 72 6f 77 73 20 69 6e |clear 16 rows in|
00000a80 20 61 64 61 70 74 6f 72 0d 04 1a 0e 2e 63 6c 65 | adaptor.....cle|
00000a90 61 72 6c 6f 6f 70 0d 04 24 0e 53 54 59 20 72 6f |arloop..$.STY ro|
00000aa0 77 72 65 67 0d 04 2e 0f 53 54 41 20 64 61 74 61 |wreg....STA data|
00000ab0 72 65 67 0d 04 38 07 44 45 59 0d 04 42 11 42 50 |reg..8.DEY..B.BP|
00000ac0 4c 20 63 6c 65 61 72 6c 6f 6f 70 0d 04 4c 35 53 |L clearloop..L5S|
00000ad0 54 41 20 73 74 61 74 63 6c 72 20 5c 20 63 6c 65 |TA statclr \ cle|
00000ae0 61 72 20 73 74 61 74 75 73 20 66 6c 61 67 73 20 |ar status flags |
00000af0 62 65 66 6f 72 65 20 72 65 74 75 72 6e 69 6e 67 |before returning|
00000b00 0d 04 56 07 50 4c 41 0d 04 60 13 54 41 59 20 5c |..V.PLA..`.TAY \|
00000b10 20 72 65 73 74 6f 72 65 20 59 0d 04 6a 07 50 4c | restore Y..j.PL|
00000b20 41 0d 04 74 13 54 41 58 20 5c 20 72 65 73 74 6f |A..t.TAX \ resto|
00000b30 72 65 20 58 0d 04 7e 07 50 4c 41 0d 04 88 3d 53 |re X..~.PLA...=S|
00000b40 54 41 20 73 61 76 65 72 65 67 20 5c 20 72 65 73 |TA savereg \ res|
00000b50 74 6f 72 65 20 69 6e 74 65 72 72 75 70 74 20 61 |tore interrupt a|
00000b60 63 63 75 6d 75 6c 61 74 6f 72 20 73 61 76 65 20 |ccumulator save |
00000b70 72 65 67 69 73 74 65 72 0d 04 92 1f 52 54 49 20 |register....RTI |
00000b80 5c 20 72 65 74 75 72 6e 20 66 72 6f 6d 20 69 6e |\ return from in|
00000b90 74 65 72 72 75 70 74 0d 04 9c 0d 2e 70 72 69 6e |terrupt.....prin|
00000ba0 74 62 63 64 0d 04 a6 07 50 48 41 0d 04 b0 09 4c |tbcd....PHA....L|
00000bb0 53 52 20 41 0d 04 ba 09 4c 53 52 20 41 0d 04 c4 |SR A....LSR A...|
00000bc0 09 4c 53 52 20 41 0d 04 ce 09 4c 53 52 20 41 0d |.LSR A....LSR A.|
00000bd0 04 d8 0e 4a 53 52 20 6e 79 62 62 6c 65 0d 04 e2 |...JSR nybble...|
00000be0 07 50 4c 41 0d 04 ec 0b 2e 6e 79 62 62 6c 65 0d |.PLA.....nybble.|
00000bf0 04 f6 17 80 20 23 26 30 46 20 5c 20 64 65 63 69 |.... #&0F \ deci|
00000c00 6d 61 6c 20 31 35 0d 05 00 07 53 45 44 0d 05 0a |mal 15....SED...|
00000c10 07 43 4c 43 0d 05 14 1a 41 44 43 20 23 26 39 30 |.CLC....ADC #&90|
00000c20 20 5c 20 64 65 63 69 6d 61 6c 20 31 34 34 0d 05 | \ decimal 144..|
00000c30 1e 19 41 44 43 20 23 26 34 30 20 5c 20 64 65 63 |..ADC #&40 \ dec|
00000c40 69 6d 61 6c 20 36 34 0d 05 28 07 43 4c 44 0d 05 |imal 64..(.CLD..|
00000c50 32 0e 4a 4d 50 20 6f 73 77 72 63 68 0d 05 3c 0c |2.JMP oswrch..<.|
00000c60 2e 63 6f 75 6e 74 65 72 0d 05 46 0c 45 51 55 44 |.counter..F.EQUD|
00000c70 20 26 30 30 0d 05 50 0d 2e 6f 6c 64 69 72 71 32 | &00..P..oldirq2|
00000c80 76 0d 05 5a 0c 45 51 55 57 20 26 30 30 0d 05 64 |v..Z.EQUW &00..d|
00000c90 05 5d 0d 05 6e 05 ed 0d 05 78 05 e1 0d ff |.]..n....x....|
00000c9e 
12-03-89/Counter.m0
12-03-89/Counter.m1
12-03-89/Counter.m2
12-03-89/Counter.m4
12-03-89/Counter.m5
.