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Patch/ThePatch/TechNote
This website contains an archive of files for the Acorn Electron, BBC Micro, Acorn Archimedes, Commodore 16 and Commodore 64 computers, which Dominic Ford has rescued from his private collection of floppy disks and cassettes.
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File contents
Technical note for RISC OS 3.70 and StrongARM, 24-Oct-96
--------------------------------------------------------
You do not need to read this note in order to use the supplied patches;
read the ReadMe file instead. This note is for those who develop code
for RISC OS.
The SA110 (of revision less than 3, as specified in the ARM ID register)
has a bug in the User Register Store Multiple instruction (STM^). This is
the STM that is used to store user mode registers while in a privileged
mode. If the STM^ is executed while a data cache fill is completing the
store address for all but the first register may be wrong.
This should not affect any application or transient code (which will
execute in user mode), nor typical module code, but may affect a few
modules.
If you use STM^ in a module that is designed to work with StrongARM, we
recommend the following workaround for the problem:
Split the STM^ into a standard STM for the non banked registers
followed by an STM^ for the banked registers, adjusting the base
register afterwards as necessary.
A typical example follows:
;privileged mode
STMIA r0,{r1-r14}^
becomes:
;privileged mode
STMIA r0!,{r1-r12} ;store non-banked registers, writeback allowed
STMIA r0,{r13,r14}^ ;store banked registers
SUB r0,r0,#12*4 ;adjust base register back
The banked registers are R13 and R14 (it is extremely unlikely that FIQ
code would perform an STM^, since the extra banked registers are
precisely to avoid this need). It may be possible to optimise the base
register adjustment into the following code, depending on how the base
register is used subsequently.
Note that this sequence is non-atomic and does manipulate the base
register value. This is unlikely to be an issue, but the effect of an
interrupt (if enabled) during this sequence may need to be borne in mind.
Similar workarounds apply to other cases. However, you should note the
following standard ARM coding considerations:
- The first (non-^) STM cannot use writeback if the base register is in
the store list; this is unlikely, because it is not particularly
useful to store the base of the stored block in the block.
- The STM^ must not use writeback.
- If the base register is one of the banked registers, then a NOP
should precede the SUB instruction (since the SUB then uses a banked
register).
00000000 0a 54 65 63 68 6e 69 63 61 6c 20 6e 6f 74 65 20 |.Technical note |
00000010 66 6f 72 20 52 49 53 43 20 4f 53 20 33 2e 37 30 |for RISC OS 3.70|
00000020 20 61 6e 64 20 53 74 72 6f 6e 67 41 52 4d 2c 20 | and StrongARM, |
00000030 32 34 2d 4f 63 74 2d 39 36 0a 2d 2d 2d 2d 2d 2d |24-Oct-96.------|
00000040 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d |----------------|
*
00000070 2d 2d 0a 0a 59 6f 75 20 64 6f 20 6e 6f 74 20 6e |--..You do not n|
00000080 65 65 64 20 74 6f 20 72 65 61 64 20 74 68 69 73 |eed to read this|
00000090 20 6e 6f 74 65 20 69 6e 20 6f 72 64 65 72 20 74 | note in order t|
000000a0 6f 20 75 73 65 20 74 68 65 20 73 75 70 70 6c 69 |o use the suppli|
000000b0 65 64 20 70 61 74 63 68 65 73 3b 0a 72 65 61 64 |ed patches;.read|
000000c0 20 74 68 65 20 52 65 61 64 4d 65 20 66 69 6c 65 | the ReadMe file|
000000d0 20 69 6e 73 74 65 61 64 2e 20 54 68 69 73 20 6e | instead. This n|
000000e0 6f 74 65 20 69 73 20 66 6f 72 20 74 68 6f 73 65 |ote is for those|
000000f0 20 77 68 6f 20 64 65 76 65 6c 6f 70 20 63 6f 64 | who develop cod|
00000100 65 0a 66 6f 72 20 52 49 53 43 20 4f 53 2e 0a 0a |e.for RISC OS...|
00000110 54 68 65 20 53 41 31 31 30 20 28 6f 66 20 72 65 |The SA110 (of re|
00000120 76 69 73 69 6f 6e 20 6c 65 73 73 20 74 68 61 6e |vision less than|
00000130 20 33 2c 20 61 73 20 73 70 65 63 69 66 69 65 64 | 3, as specified|
00000140 20 69 6e 20 74 68 65 20 41 52 4d 20 49 44 20 72 | in the ARM ID r|
00000150 65 67 69 73 74 65 72 29 0a 68 61 73 20 61 20 62 |egister).has a b|
00000160 75 67 20 69 6e 20 74 68 65 20 55 73 65 72 20 52 |ug in the User R|
00000170 65 67 69 73 74 65 72 20 53 74 6f 72 65 20 4d 75 |egister Store Mu|
00000180 6c 74 69 70 6c 65 20 69 6e 73 74 72 75 63 74 69 |ltiple instructi|
00000190 6f 6e 20 28 53 54 4d 5e 29 2e 20 54 68 69 73 20 |on (STM^). This |
000001a0 69 73 0a 74 68 65 20 53 54 4d 20 74 68 61 74 20 |is.the STM that |
000001b0 69 73 20 75 73 65 64 20 74 6f 20 73 74 6f 72 65 |is used to store|
000001c0 20 75 73 65 72 20 6d 6f 64 65 20 72 65 67 69 73 | user mode regis|
000001d0 74 65 72 73 20 77 68 69 6c 65 20 69 6e 20 61 20 |ters while in a |
000001e0 70 72 69 76 69 6c 65 67 65 64 0a 6d 6f 64 65 2e |privileged.mode.|
000001f0 20 49 66 20 74 68 65 20 53 54 4d 5e 20 69 73 20 | If the STM^ is |
00000200 65 78 65 63 75 74 65 64 20 77 68 69 6c 65 20 61 |executed while a|
00000210 20 64 61 74 61 20 63 61 63 68 65 20 66 69 6c 6c | data cache fill|
00000220 20 69 73 20 63 6f 6d 70 6c 65 74 69 6e 67 20 74 | is completing t|
00000230 68 65 0a 73 74 6f 72 65 20 61 64 64 72 65 73 73 |he.store address|
00000240 20 66 6f 72 20 61 6c 6c 20 62 75 74 20 74 68 65 | for all but the|
00000250 20 66 69 72 73 74 20 72 65 67 69 73 74 65 72 20 | first register |
00000260 6d 61 79 20 62 65 20 77 72 6f 6e 67 2e 0a 0a 54 |may be wrong...T|
00000270 68 69 73 20 73 68 6f 75 6c 64 20 6e 6f 74 20 61 |his should not a|
00000280 66 66 65 63 74 20 61 6e 79 20 61 70 70 6c 69 63 |ffect any applic|
00000290 61 74 69 6f 6e 20 6f 72 20 74 72 61 6e 73 69 65 |ation or transie|
000002a0 6e 74 20 63 6f 64 65 20 28 77 68 69 63 68 20 77 |nt code (which w|
000002b0 69 6c 6c 0a 65 78 65 63 75 74 65 20 69 6e 20 75 |ill.execute in u|
000002c0 73 65 72 20 6d 6f 64 65 29 2c 20 6e 6f 72 20 74 |ser mode), nor t|
000002d0 79 70 69 63 61 6c 20 6d 6f 64 75 6c 65 20 63 6f |ypical module co|
000002e0 64 65 2c 20 62 75 74 20 6d 61 79 20 61 66 66 65 |de, but may affe|
000002f0 63 74 20 61 20 66 65 77 0a 6d 6f 64 75 6c 65 73 |ct a few.modules|
00000300 2e 0a 0a 49 66 20 79 6f 75 20 75 73 65 20 53 54 |...If you use ST|
00000310 4d 5e 20 69 6e 20 61 20 6d 6f 64 75 6c 65 20 74 |M^ in a module t|
00000320 68 61 74 20 69 73 20 64 65 73 69 67 6e 65 64 20 |hat is designed |
00000330 74 6f 20 77 6f 72 6b 20 77 69 74 68 20 53 74 72 |to work with Str|
00000340 6f 6e 67 41 52 4d 2c 20 77 65 0a 72 65 63 6f 6d |ongARM, we.recom|
00000350 6d 65 6e 64 20 74 68 65 20 66 6f 6c 6c 6f 77 69 |mend the followi|
00000360 6e 67 20 77 6f 72 6b 61 72 6f 75 6e 64 20 66 6f |ng workaround fo|
00000370 72 20 74 68 65 20 70 72 6f 62 6c 65 6d 3a 0a 0a |r the problem:..|
00000380 20 20 20 20 53 70 6c 69 74 20 74 68 65 20 53 54 | Split the ST|
00000390 4d 5e 20 69 6e 74 6f 20 61 20 73 74 61 6e 64 61 |M^ into a standa|
000003a0 72 64 20 53 54 4d 20 66 6f 72 20 74 68 65 20 6e |rd STM for the n|
000003b0 6f 6e 20 62 61 6e 6b 65 64 20 72 65 67 69 73 74 |on banked regist|
000003c0 65 72 73 0a 20 20 20 20 66 6f 6c 6c 6f 77 65 64 |ers. followed|
000003d0 20 62 79 20 61 6e 20 53 54 4d 5e 20 66 6f 72 20 | by an STM^ for |
000003e0 74 68 65 20 62 61 6e 6b 65 64 20 72 65 67 69 73 |the banked regis|
000003f0 74 65 72 73 2c 20 61 64 6a 75 73 74 69 6e 67 20 |ters, adjusting |
00000400 74 68 65 20 62 61 73 65 0a 20 20 20 20 72 65 67 |the base. reg|
00000410 69 73 74 65 72 20 61 66 74 65 72 77 61 72 64 73 |ister afterwards|
00000420 20 61 73 20 6e 65 63 65 73 73 61 72 79 2e 0a 0a | as necessary...|
00000430 41 20 74 79 70 69 63 61 6c 20 65 78 61 6d 70 6c |A typical exampl|
00000440 65 20 66 6f 6c 6c 6f 77 73 3a 0a 0a 20 20 20 20 |e follows:.. |
00000450 3b 70 72 69 76 69 6c 65 67 65 64 20 6d 6f 64 65 |;privileged mode|
00000460 20 20 0a 20 20 20 20 53 54 4d 49 41 20 72 30 2c | . STMIA r0,|
00000470 7b 72 31 2d 72 31 34 7d 5e 0a 0a 62 65 63 6f 6d |{r1-r14}^..becom|
00000480 65 73 3a 0a 0a 20 20 20 20 3b 70 72 69 76 69 6c |es:.. ;privil|
00000490 65 67 65 64 20 6d 6f 64 65 0a 20 20 20 20 53 54 |eged mode. ST|
000004a0 4d 49 41 20 72 30 21 2c 7b 72 31 2d 72 31 32 7d |MIA r0!,{r1-r12}|
000004b0 20 20 20 20 3b 73 74 6f 72 65 20 6e 6f 6e 2d 62 | ;store non-b|
000004c0 61 6e 6b 65 64 20 72 65 67 69 73 74 65 72 73 2c |anked registers,|
000004d0 20 77 72 69 74 65 62 61 63 6b 20 61 6c 6c 6f 77 | writeback allow|
000004e0 65 64 0a 20 20 20 20 53 54 4d 49 41 20 72 30 2c |ed. STMIA r0,|
000004f0 7b 72 31 33 2c 72 31 34 7d 5e 20 20 20 3b 73 74 |{r13,r14}^ ;st|
00000500 6f 72 65 20 62 61 6e 6b 65 64 20 72 65 67 69 73 |ore banked regis|
00000510 74 65 72 73 0a 20 20 20 20 53 55 42 20 20 20 72 |ters. SUB r|
00000520 30 2c 72 30 2c 23 31 32 2a 34 20 20 20 20 20 3b |0,r0,#12*4 ;|
00000530 61 64 6a 75 73 74 20 62 61 73 65 20 72 65 67 69 |adjust base regi|
00000540 73 74 65 72 20 62 61 63 6b 0a 0a 54 68 65 20 62 |ster back..The b|
00000550 61 6e 6b 65 64 20 72 65 67 69 73 74 65 72 73 20 |anked registers |
00000560 61 72 65 20 52 31 33 20 61 6e 64 20 52 31 34 20 |are R13 and R14 |
00000570 28 69 74 20 69 73 20 65 78 74 72 65 6d 65 6c 79 |(it is extremely|
00000580 20 75 6e 6c 69 6b 65 6c 79 20 74 68 61 74 20 46 | unlikely that F|
00000590 49 51 0a 63 6f 64 65 20 77 6f 75 6c 64 20 70 65 |IQ.code would pe|
000005a0 72 66 6f 72 6d 20 61 6e 20 53 54 4d 5e 2c 20 73 |rform an STM^, s|
000005b0 69 6e 63 65 20 74 68 65 20 65 78 74 72 61 20 62 |ince the extra b|
000005c0 61 6e 6b 65 64 20 72 65 67 69 73 74 65 72 73 20 |anked registers |
000005d0 61 72 65 0a 70 72 65 63 69 73 65 6c 79 20 74 6f |are.precisely to|
000005e0 20 61 76 6f 69 64 20 74 68 69 73 20 6e 65 65 64 | avoid this need|
000005f0 29 2e 20 49 74 20 6d 61 79 20 62 65 20 70 6f 73 |). It may be pos|
00000600 73 69 62 6c 65 20 74 6f 20 6f 70 74 69 6d 69 73 |sible to optimis|
00000610 65 20 74 68 65 20 62 61 73 65 0a 72 65 67 69 73 |e the base.regis|
00000620 74 65 72 20 61 64 6a 75 73 74 6d 65 6e 74 20 69 |ter adjustment i|
00000630 6e 74 6f 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e |nto the followin|
00000640 67 20 63 6f 64 65 2c 20 64 65 70 65 6e 64 69 6e |g code, dependin|
00000650 67 20 6f 6e 20 68 6f 77 20 74 68 65 20 62 61 73 |g on how the bas|
00000660 65 0a 72 65 67 69 73 74 65 72 20 69 73 20 75 73 |e.register is us|
00000670 65 64 20 73 75 62 73 65 71 75 65 6e 74 6c 79 2e |ed subsequently.|
00000680 0a 0a 4e 6f 74 65 20 74 68 61 74 20 74 68 69 73 |..Note that this|
00000690 20 73 65 71 75 65 6e 63 65 20 69 73 20 6e 6f 6e | sequence is non|
000006a0 2d 61 74 6f 6d 69 63 20 61 6e 64 20 64 6f 65 73 |-atomic and does|
000006b0 20 6d 61 6e 69 70 75 6c 61 74 65 20 74 68 65 20 | manipulate the |
000006c0 62 61 73 65 0a 72 65 67 69 73 74 65 72 20 76 61 |base.register va|
000006d0 6c 75 65 2e 20 54 68 69 73 20 69 73 20 75 6e 6c |lue. This is unl|
000006e0 69 6b 65 6c 79 20 74 6f 20 62 65 20 61 6e 20 69 |ikely to be an i|
000006f0 73 73 75 65 2c 20 62 75 74 20 74 68 65 20 65 66 |ssue, but the ef|
00000700 66 65 63 74 20 6f 66 20 61 6e 0a 69 6e 74 65 72 |fect of an.inter|
00000710 72 75 70 74 20 28 69 66 20 65 6e 61 62 6c 65 64 |rupt (if enabled|
00000720 29 20 64 75 72 69 6e 67 20 74 68 69 73 20 73 65 |) during this se|
00000730 71 75 65 6e 63 65 20 6d 61 79 20 6e 65 65 64 20 |quence may need |
00000740 74 6f 20 62 65 20 62 6f 72 6e 65 20 69 6e 20 6d |to be borne in m|
00000750 69 6e 64 2e 0a 0a 53 69 6d 69 6c 61 72 20 77 6f |ind...Similar wo|
00000760 72 6b 61 72 6f 75 6e 64 73 20 61 70 70 6c 79 20 |rkarounds apply |
00000770 74 6f 20 6f 74 68 65 72 20 63 61 73 65 73 2e 20 |to other cases. |
00000780 48 6f 77 65 76 65 72 2c 20 79 6f 75 20 73 68 6f |However, you sho|
00000790 75 6c 64 20 6e 6f 74 65 20 74 68 65 0a 66 6f 6c |uld note the.fol|
000007a0 6c 6f 77 69 6e 67 20 73 74 61 6e 64 61 72 64 20 |lowing standard |
000007b0 41 52 4d 20 63 6f 64 69 6e 67 20 63 6f 6e 73 69 |ARM coding consi|
000007c0 64 65 72 61 74 69 6f 6e 73 3a 0a 0a 20 20 2d 20 |derations:.. - |
000007d0 54 68 65 20 66 69 72 73 74 20 28 6e 6f 6e 2d 5e |The first (non-^|
000007e0 29 20 53 54 4d 20 63 61 6e 6e 6f 74 20 75 73 65 |) STM cannot use|
000007f0 20 77 72 69 74 65 62 61 63 6b 20 69 66 20 74 68 | writeback if th|
00000800 65 20 62 61 73 65 20 72 65 67 69 73 74 65 72 20 |e base register |
00000810 69 73 20 69 6e 0a 20 20 20 20 74 68 65 20 73 74 |is in. the st|
00000820 6f 72 65 20 6c 69 73 74 3b 20 74 68 69 73 20 69 |ore list; this i|
00000830 73 20 75 6e 6c 69 6b 65 6c 79 2c 20 62 65 63 61 |s unlikely, beca|
00000840 75 73 65 20 69 74 20 69 73 20 6e 6f 74 20 70 61 |use it is not pa|
00000850 72 74 69 63 75 6c 61 72 6c 79 0a 20 20 20 20 75 |rticularly. u|
00000860 73 65 66 75 6c 20 74 6f 20 73 74 6f 72 65 20 74 |seful to store t|
00000870 68 65 20 62 61 73 65 20 6f 66 20 74 68 65 20 73 |he base of the s|
00000880 74 6f 72 65 64 20 62 6c 6f 63 6b 20 69 6e 20 74 |tored block in t|
00000890 68 65 20 62 6c 6f 63 6b 2e 0a 0a 20 20 2d 20 54 |he block... - T|
000008a0 68 65 20 53 54 4d 5e 20 6d 75 73 74 20 6e 6f 74 |he STM^ must not|
000008b0 20 75 73 65 20 77 72 69 74 65 62 61 63 6b 2e 0a | use writeback..|
000008c0 0a 20 20 2d 20 49 66 20 74 68 65 20 62 61 73 65 |. - If the base|
000008d0 20 72 65 67 69 73 74 65 72 20 69 73 20 6f 6e 65 | register is one|
000008e0 20 6f 66 20 74 68 65 20 62 61 6e 6b 65 64 20 72 | of the banked r|
000008f0 65 67 69 73 74 65 72 73 2c 20 74 68 65 6e 20 61 |egisters, then a|
00000900 20 4e 4f 50 0a 20 20 20 20 73 68 6f 75 6c 64 20 | NOP. should |
00000910 70 72 65 63 65 64 65 20 74 68 65 20 53 55 42 20 |precede the SUB |
00000920 69 6e 73 74 72 75 63 74 69 6f 6e 20 28 73 69 6e |instruction (sin|
00000930 63 65 20 74 68 65 20 53 55 42 20 74 68 65 6e 20 |ce the SUB then |
00000940 75 73 65 73 20 61 20 62 61 6e 6b 65 64 0a 20 20 |uses a banked. |
00000950 20 20 72 65 67 69 73 74 65 72 29 2e 0a | register)..|
0000095d 
.