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September/FastDiv/FastDiv
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| Tape/disk: | Home » Archimedes archive » Archimedes World » AW-1996-03-Disc 2.adf » !AcornAns_AcornAns |
| Filename: | September/FastDiv/FastDiv |
| Read OK: | ✔ |
| File size: | 34D7 bytes |
| Load address: | 0000 |
| Exec address: | 0000 |
Duplicates
There is 1 duplicate copy of this file in the archive:
- Archimedes archive » Archimedes World » AW-1996-03-Disc 2.adf » !AcornAns_AcornAns » September/FastDiv/FastDiv
- Archimedes archive » Archimedes World » AW-1995-05-Disc1.adf » AWMay95_1 » InTheMag/AcornAns/FastDiv
File contents
10REM >FASTDIVbsc
20REM Fast DIV/MOD with a constant number
30REM code fragment to test fastdiv/mod code generation
40REM Author: Samuel K.R. Smith
50REM Heavily MODIFIED by Michael Rozdoba, February '95
60REM (fixes & additional modifications)
70
80ONERROR:PROCerr:END
90MODE 0
100
110spoolpath$ = "FDdemo"
120spool%=FALSE
130IF spool% OSCLI("Spool "+spoolpath$)
140
150PRINT '"Fast Integer Division Code for arbitrary CONSTANT Divisor -"
160PRINT "Compilation & testing:"'
170PRINT "This program lists the divisors it is testing & disassembles each routine,"
180PRINT "each of which calculates R0 = R2 DIV divisor, R1 = R2 MOD divisor."
190PRINT "If it finds an error it prints the details and waits for a key press."''
200
210DIM code% &400
220r0=0:r1=1:r2=2:r3=3
230
240Q%=1000
250R%=&7FFFFFFF-Q%
260S%=&80000000+Q%
270maxc%=0: nmaxc%=0: totc%=0: cnt%=0
280
290Zbase%=1
300Zrange%=100000
310
320Z%=Zbase%
330REPEAT
340 PROCcheck( Z%,-Q%,Q%, 1)
350 PROCcheck(-Z%,-Q%,Q%, 2)
360 PROCcheck( Z%,R%,&7FFFFFFF, 0)
370 PROCcheck(-Z%,R%,&7FFFFFFF, 0)
380 PROCcheck( Z%,&80000000,S%, 0)
390 PROCcheck(-Z%,&80000000,S%, 0)
400 PROCcheck( Z%,-Q%,Q%, 100+0)
410 PROCcheck(-Z%,-Q%,Q%, 100-1)
420 cnt% += 1
430 l% =(aft%-fore%)/4
440 totc% += l%
450 IF l%>maxc% THEN
460 maxc% = l%
470 nmaxc%= Z%
480 ENDIF
490 PRINT"Current max code length ";maxc%;" instructions for divisor ";FNnstr(nmaxc%)
500 PRINT"Average code length ";totc%/cnt%;" instructions"''
510Z%+=1
520UNTIL Z%=Zbase%+Zrange%
530ERROR 1, "All done"
540
550END
560
570DEFPROCcheck(N%,START%,FINISH%, report%)
580LOCAL l%, rnd%
590PROCasstst(N%):REM produce the code then test it!
600
610IF report%>50 rnd%=TRUE:report%-=100 ELSE rnd%=FALSE
620IF report% < 1 PRINT ;", ";FNnstr(N%);
630IF report% =-1 PRINT
640IF report%=1 THEN
650 PRINT"Checking division by &";~N%;" = ";N%
660 l% =(aft%-fore%)/4
670 PRINT"Using code, length ";l%;" instructions:"
680 PROCdis(fore%, aft%)
690ENDIF
700IF report%=2 PRINT"Further checks for ";FNnstr(N%);
710
720IF rnd% A%=RND(-1)
730FOR F%=START% TO FINISH% STEP 1
740 IF rnd% THEN
750 IF RND(2)=1 C%=RND(&7FFFFFFF)-&40000000 ELSE C%=RND(&0007FFFF)-&00040000
760 ELSE
770 C%=F%
780 ENDIF
790 A%=USR(code%):B%=!r%
800 D%=C% DIV N%:E%=C% MOD N%
810 IF (A%<>D%)OR(B%<>E%) THEN
820 PRINT"Error Found: ";~C%;" DIV ";~N%;"=";~A%;" ";
830 PRINT;~C%;" MOD ";~N%;"=";~B%;" should be ";~D%;" and ";~E%
840 IF spool%=FALSE G=GET
850 ENDIF
860NEXT
870ENDPROC
880
890DEFPROCasstst(n%)
900r0=0:r1=1:r2=2:r3=3:r4=4:r5=5:lr=14
910
920REM require workReg if n% can't be expressed as a valid immediate const
930workR=r4
940
950signpresR=r3
960
970FOR pass%=0 TO 2 STEP 2
980P%=code%
990[ OPT pass%
1000.fore% OPT FNFastDiv(r0,r1,r2,n%,signpresR,workR,pass%)
1010.aft% STR r1,r%
1020 MOV pc,lr
1030.r% EQUD 0
1040]
1050NEXT
1060ENDPROC
1070
1080REMFast Divide
1090REM-----------
1100DEFFNFastDiv(outq%,outr%,num%,const%,signpres%,work%,pass%)
1110LOCAL n%
1120REM To not pass, signpres, use -1 instead of valid register const.
1130
1140IF const%=0 THEN PRINT"FastDiv:Attempt to code division by ZERO !":STOP
1150
1160REM Preserve the sign of const%
1170IF const%<0 THEN nsignpres=-1:const%=-const% ELSE nsignpres=+1
1180power_of_2 =FNpowerof2(const%)
1190IF FNimop2(const%)<>-1 THEN work%=-1 :REM if can be represented as an immediate constant, no need for work% register
1200
1210IF FNInvReg(outq%) OR FNInvReg(outr%) OR FNInvReg(num%) THEN
1220 PRINT "FastDiv:Invalid Register":STOP
1230ENDIF
1240IF outq%=outr% OR outq%=num% OR num%=outr% THEN
1250 PRINT"FastDiv:q,r,num registers Must be different":STOP
1260ENDIF
1270IF outq%=signpres% OR outr%=signpres% OR num%=signpres% THEN
1280 IF signpres%<>-1 THEN PRINT"FastDiv:Invalid signpres register":STOP
1290ENDIF
1300IF outq%=work% OR outr%=work% OR num%=work% OR signpres%=work% THEN
1310 IF work%<>-1 THEN PRINT"FastDiv:Invalid work register":STOP
1320ENDIF
1330
1340IF const%=1 THEN
1350 IF nsignpres=+1 THEN
1360 [OPT pass%
1370 MOV outr%, #0
1380 MOV outq%, num%
1390 ]
1400 ELSE
1410 [OPT pass%
1420 MOV outr%, #0
1430 RSB outq%, num%, #0
1440 ]
1450 ENDIF
1460=pass%
1470ENDIF
1480
1490REM set bit31 of this reg to NOT(sign of num%)
1500IF NOT FNInvReg(signpres%) THEN
1510 [OPT pass%
1520 ANDS signpres%,num%,#&80000000 ; save sign of num
1530 RSBNE num%,num%,#0; make num positive
1540 ]
1550ENDIF
1560
1570REM Carry out Fast Integer Division
1580IF const%=(1<<power_of_2) THEN
1590 REM division by a power of 2
1600 [OPT pass%
1610 MOV outq%,num%,lsr #power_of_2
1620 SUB outr%,num%,outq%,lsl #power_of_2
1630 ]
1640ELSE
1650
1660 subflag%=FALSE
1670
1680 IF NOT FNInvReg(work%) THEN
1690 [OPT FNmegamov(work%, const%, pass%)
1700 ]
1710 ENDIF
1720
1730 npower_of_2=power_of_2
1740 const%=const%>>npower_of_2
1750
1760 t1%=1:s%=0:m%=0
1770 WHILE (t1%<>0) AND (m%<=32)
1780 IF (t1%>=const%) THEN t1%=t1%-const%:s%+=1
1790 IF (t1%<>0) THEN t1%=(t1%<<1)+1:s%=s%<<1:m%=m%+1
1800 ENDWHILE
1810 t1%=FNpowerof2(s%)
1820 power_of_2=power_of_2 - t1%
1830 s%=s% >> t1%
1840 IF s%=1 THEN
1850 REM MOV outq%,num% (done by joining with next instruction!)
1860 ELSE
1870 [OPT FNFastDivAid(outq%,num%,s%,pass%)
1880 ]
1890 ENDIF
1900 ls%=FNbitpatlen(s%):REM calc:ls (len:s):2^(ls-1)<= s <2^(ls),ls<=m
1910 t1%=m%+1:REM generate code for sssss.... to 32 bits
1920 WHILE t1%<32
1930 IF s%=1 THEN
1940 s%=0
1950 [OPT pass%
1960 ADD outq%,num%,num%,LSR #t1%
1970 ]
1980 ELSE
1990 [OPT pass%
2000 ADD outq%,outq%,outq%,LSR #t1%
2010 ]
2020 ENDIF
2030 t1%=t1%*2
2040 ENDWHILE
2050 IF s%=1 THEN
2060 REM Used by some large divisors (eg &7ffffff1)
2070 [OPT pass%
2080 MOV outq%, num%
2090 ]
2100 ENDIF
2110 power_of_2=power_of_2+m%-ls%+2
2120 IF power_of_2 <>0 THEN
2130 [OPT pass%
2140 MOV outq%,outq%,LSR #power_of_2 ;gen final shift
2150 ]
2160 ENDIF
2170 IF const%=1 THEN PRINT"FastDiv:Sorry Program Error 1, please report":STOP
2180 [OPT FNFastMul(outr%,outq%,const%,pass%)
2190 ]
2200 const%=const% << npower_of_2
2210 IF npower_of_2 <>0 THEN
2220 [OPT pass%
2230 SUBS outr%,num%,outr%,LSL# npower_of_2
2240 ]
2250 ELSE
2260 [OPT pass%
2270 SUBS outr%,num%,outr%
2280 ]
2290 ENDIF
2300 IF FNInvReg(work%) THEN
2310 IF subflag% THEN
2320 [OPT pass%
2330 SUBMI outq%,outq%,#1
2340 ADDMI outr%,outr%,#const%
2350 ]
2360 ENDIF
2370 [OPT pass%
2380 CMP outr%,#const%
2390 ADDGE outq%,outq%,#1
2400 SUBGE outr%,outr%,#const%
2410 ]
2420 ELSE
2430 IF subflag% THEN
2440 [OPT pass%
2450 SUBMI outq%,outq%,#1
2460 ADDMI outr%,outr%,work%
2470 ]
2480 ENDIF
2490 [OPT pass%
2500 CMP outr%,work%
2510 ADDGE outq%,outq%,#1
2520 SUBGE outr%,outr%,work%
2530 ]
2540 ENDIF
2550ENDIF
2560
2570REM change sign of answer if const%<0 at start
2580IF FNInvReg(signpres%) THEN
2590 IF (nsignpres=-1) THEN
2600 [OPT pass%
2610 RSB outq%,outq%,#0
2620 ]
2630 ENDIF
2640ELSE
2650 [OPT pass%
2660 TEQS signpres%,#&80000000 ; get stored sign
2670 RSBEQ num%,num%,#0; remove if don't want to preserve original no.
2680 RSBEQ outr%,outr%,#0
2690 ]
2700 IF (nsignpres=-1) THEN
2710 [OPT pass%
2720 RSBNE outq%,outq%,#0
2730 ]
2740 ELSE
2750 [OPT pass%
2760 RSBEQ outq%,outq%,#0
2770 ]
2780 ENDIF
2790ENDIF
2800
2810=pass%
2820
2830REMFast Divide Aider:- For Working details see h.FastDiv
2840REM-----------------
2850DEFFNFastDivAid(Rb,Ra,const%,pass%)
2860REM
2870LOCAL n%,ls%
2880LOCAL divinst$
2890IF const% = 1 OR const%=0:PRINT"FastDivAid:Logic error 1, can't by 1 or 0":STOP
2900IF const%<0 THEN ERROR 0,"FastDivAid:Logic error 2 found"
2910IF Rb=Ra THEN PRINT"FastDivAid:Registers Must be different":STOP
2920IF FNInvReg(Rb) OR FNInvReg(Ra) THEN PRINT "FastDivAid:Invalid Register":STOP
2930
2940REM Find the length of bit pattern s, from the first 1
2950ls%=FNbitpatlen(const%)
2960
2970CASE (const% AND 3) OF
2980WHEN 0,2:REM ie sb of form s = s1 * 2^n, n>1
2990 PRINT "FastDivAid:Program logic error 3":STOP
3000WHEN 1: REM ie s of form s = s1 * 2^n +1, s1 odd, n>1
3010 const%-=1
3020 divinst$="ADD"
3030WHEN 3:REM ie s of form s = s1 * 2^n -1, s1 odd, n>1
3040 const%+=1
3050 divinst$="SUB"
3060 subflag%=TRUE
3070ENDCASE
3080const%=const% >>> FNpowerof2(const%)
3090IF const%=1 THEN
3100 IF (divinst$="SUB") THEN
3110 IF ls%<=1 THEN PRINT"FastDivAid:Logic Error 4":STOP
3120 [OPT pass%
3130 ADD Rb,Ra,Ra ;<---FASTDIVaid Gen
3140 SUB Rb,Rb,Ra,LSR#ls% -1 ;<---FASTDIVaid Gen
3150 ]
3160 ELSE
3170 [OPT pass%
3180 ADD Rb,Ra,Ra, LSR #ls%-1 ;<---FASTDIVaid Gen
3190 ]
3200 ENDIF
3210ELSE
3220 IF (divinst$="SUB") THEN
3230 [OPT FNFastDivAid(Rb,Ra,const%,pass%)
3240 SUB Rb,Rb,Ra, LSR #ls%-1 ;<---FASTDIVaid Gen
3250 ]
3260 ELSE
3270 [OPT FNFastDivAid(Rb,Ra,const%,pass%)
3280 ADD Rb,Rb,Ra, LSR #ls%-1 ;<---FASTDIVaid Gen
3290 ]
3300 ENDIF
3310ENDIF
3320
3330=pass%
3340
3350REMFast Multiply
3360REM--------------
3370REM//initialise macro with
3380REM//registers: result ,number to be multiplied by constant
3390REM//followed by: the constant you wish to fast multiply by
3400REM// generates code to solve to get Rb=Ra * s
3410REM//when Ra,Rb are registers and s=constant to multiply by
3420REM//if s=0 or s=1 macro aborts !!!! (Try MOV Rb,Ra or MOV Rb,#0 !!)
3430REM//Comment: Ra is preserved after the code
3440REM//Order of components to use just like a standard instruction !
3450
3460DEFFNFastMul(Rb,Ra,const%,pass%)
3470REM Generate instructions for fast multiply Rb=Ra * const%
3480LOCAL n%
3490IF const%=1 OR const%=0:PRINT"FastMul:Silly FastMul by 1 or 0":STOP
3500IF Rb=Ra THEN PRINT"FastMul:Registers Must be different":STOP
3510IF FNInvReg(Rb) OR FNInvReg(Ra) THEN PRINT "FastMul:Invalid Register":STOP
3520CASE (const% AND 3) OF
3530WHEN 0,2:REM const% of form s1 * 2^n, n>1
3540 n%=FNpowerof2(const%)
3550 const%=const%/(1<<n%)
3560 IF const%=1 THEN
3570 [OPT pass%
3580 MOV Rb,Ra, LSL #n%;<------FAST MUL generated
3590 ]
3600 ELSE
3610 [OPT FNFastMul(Rb,Ra,const%,pass%)
3620 MOV Rb,Rb, LSL #n%;<------FAST MUL generated
3630 ]
3640 ENDIF
3650WHEN 1:REM const% of form s1 * 2^n +1, s1 odd, n>1
3660 const%=const%-1
3670 n%=FNpowerof2(const%)
3680 const%=const%/(1<<n%)
3690 IF const%=1 THEN
3700 [OPT pass%
3710 ADD Rb,Ra,Ra, LSL #n%;<------FAST MUL generated
3720 ]
3730 ELSE
3740 [OPT FNFastMul(Rb,Ra,const%,pass%)
3750 ADD Rb,Ra,Rb, LSL #n%;<------FAST MUL generated
3760 ]
3770 ENDIF
3780WHEN 3:REM const% of form s1 * 2^n -1, s1 odd, n>1
3790 const%=const%+1
3800 n%=FNpowerof2(const%)
3810 const%=const%/(1<<n%)
3820 IF const%=1 THEN
3830 [OPT pass%
3840 RSB Rb,Ra,Ra, LSL #n%;<------FAST MUL generated
3850 ]
3860 ELSE
3870 [OPT FNFastMul(Rb,Ra,const%,pass%)
3880 RSB Rb,Ra,Rb, LSL #n%;<------FAST MUL generated
3890 ]
3900 ENDIF
3910ENDCASE
3920=pass%
3930
3940REM Find length of bit pattern from first 1 to bit 0 position
3950DEFFNbitpatlen(S%)
3960LOCAL Scopy%,ls%
3970Scopy%=S%
3980ls%=0
3990WHILE Scopy%<>0
4000 Scopy%=Scopy%>>>1
4010 ls%+=1
4020ENDWHILE
4030=ls%
4040
4050
4060REM Find highest power of 2 which divides n
4070DEFFNpowerof2(N%)
4080LOCAL n%
4090IF N%=0 THEN =0:REM possible error
4100n%=0
4110WHILE (N% AND 1)=0:n%+=1:N%=N%>>>1:ENDWHILE
4120=n%
4130
4140REM Check out registers
4150DEFFNInvReg(reg)
4160=(reg<0 OR reg>12) :REM Unsensible registers
4170
4180REM Decompose argument into machine code immediate value operand 2
4190REM if possible, else return -1.
4200REM IE into an 8 bit chunk 'Imm' & a 4 bit rotation 'Rotate', st
4210REM 12 bit operand = Rotate<<8 + Imm,
4220REM where original argument = Imm rotated right by (2*Rotate).
4230DEF FNimop2(a%)
4240LOCAL i%, r%
4250r%=0
4260FOR i%=0 TO 30 STEP 2
4270IF (a% AND NOT 255)=0 THEN = r%ORa%
4280a% = (a%>>>30) OR (a%<<2) :REM ie rot left 2
4290r%+= 256
4300NEXT
4310= -1
4320
4330REM Recall in MOV Rn, #v%, there is a restriction on permitted v%.
4340REM Following function assembles a multi-instruction mov capable
4350REM of taking any 32-bit v%.
4360REM Aim is to achieve this using as few instructions as possible
4370REM for each value of v% (never need more than 4, of course).
4380REM
4390REM - Well, actually following isn't quite optimal:
4400REM It looks for the longest sequence of zero bits, & then splits
4410REM rest into 8 bit chunks assigning first using MOV & each
4420REM subsequent non-zero one using ORR.
4430REM If you were to repeat algo below, but looking for long seq
4440REM of 1's instead of zeros, & used a similar process to below to
4450REM build mov using MVN & BIC to specify 0's (instead of MOV & ORR
4460REM to specify 1's), this would in some cases yield better soln.
4470REM So, ideally do both & pick best.
4480REM NB That still wouldn't be optimal, but it might be close.
4490REM
4500REM Anyone know of a better way?
4510REM
4520DEF FNmegamov(a%, v%, pass%)
4530LOCAL i%, m%, r%, mi%, ml%, li%
4540IF v%=0 THEN
4550 [OPT pass%
4560 MOV a%, #0
4570 ]
4580 = pass%
4590ENDIF
4600r%=0 :REM Now need to find the longest span of zeros, allowing bit wrap from b0 to b31
4610WHILE (v%AND1)=0 :REM rotate to get a 1 into b0
4620 v% = (v%>>>31) OR (v%<<1)
4630 r%+= 1
4640ENDWHILE
4650i%=0
4660m%=1
4670ml%=0 :REM Length of longest sequence of zeros
4680REPEAT
4690 REPEAT :REM scan till get zero or all bits checked
4700 i%+= 1
4710 m% = m%<<1
4720 UNTIL (i%>31) OR ((v%ANDm%)=0)
4730 IF (i%<32) THEN
4740 li% = i% :REM start of a zero sequence
4750 REPEAT
4760 i%+= 1
4770 m% = m%<<1
4780 UNTIL (i%>31) OR ((v%ANDm%)<>0)
4790 IF (i%-li%)>ml% THEN mi%=li%:ml%=i%-li% :REM start of longest zero sequence so far
4800 ENDIF
4810UNTIL i%>31
4820IF ml%>0 THEN
4830 REM shift to get zero sequence in most significant bits of v%
4840 i% = 32-(mi%+ml%)
4850 v% = (v%>>>(32-i%)) OR (v%<<i%)
4860 r%+= i%
4870ENDIF
4880IF r%AND1 THEN
4890 REM r% must be even
4900 v% = (v%>>>31) OR (v%<<1)
4910 r%+= 1
4920ENDIF
4930
4940REM now do the move, at last!
4950i% = v%AND255
4960[OPT pass%
4970 MOV a%, #(i%>>>r%) OR (i%<<(32-r%)) :REM ie i% ror r%
4980]
4990REPEAT
5000 v% = v%>>>8
5010 IF (v%=0) THEN = pass%
5020 r% = 31 AND (r%-8)
5030 i% = v%AND255
5040 IF i% THEN
5050 [OPT pass%
5060 ORR a%, a%, #(i%>>>r%) OR (i%<<(32-r%))
5070 ]
5080 ENDIF
5090UNTIL FALSE
5100= pass%
5110
5120DEF PROCdis(a%, b%)
5130LOCAL q%, w%, q$, i%
5140FOR q%=a% TO b%-1 STEP 4
5150 SYS &40380, !q%, q% TO ,x%,y%
5160 q$=""
5170 FOR w%=x% TO x%+y%-1
5180 q$+=CHR$(?w%)
5190 NEXT
5200 i% = INSTR(q$, ";")
5210 IF i%>1 THEN
5220 FOR w%=i%-1 TO 1 STEP -1
5230 IF MID$(q$, w%, 1) <> " " THEN
5240 q$ = LEFT$(q$, w%)
5250 w%=0
5260 ENDIF
5270 NEXT
5280 ENDIF
5290 PRINT q$
5300NEXT
5310ENDPROC
5320
5330DEF FNnstr(n%)
5340IF ABS(n%)<65536 THEN
5350 = STR$(n%)
5360ELSE
5370 = "&"+STR$~(n%)
5380ENDIF
5390
5400DEF PROCerr
5410ON ERROR OFF
5420REPORT:PRINT" with code: ";ERL/10
5430IF spool% THEN
5440 *Spool
5450 spool%=FALSE
5460 OSCLI("SetType "+spoolpath$+" Text")
5470ENDIF
5480ENDPROC
� >FASTDIVbsc
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�
�� pass%=0 � 2 � 2
� P%=code%
�[ OPT pass%
�>.fore% OPT �FastDiv(r0,r1,r2,n%,signpresR,workR,pass%)
�.aft% STR r1,r%
� MOV pc,lr
.r% EQUD 0
]
�
$�
.
8�Fast Divide
B�-----------
L<ݤFastDiv(outq%,outr%,num%,const%,signpres%,work%,pass%)
V� n%
`D� To not pass, signpres, use -1 instead of valid register const.
j
t@� const%=0 � �"FastDiv:Attempt to code division by ZERO !":�
~
�!� Preserve the sign of const%
�;� const%<0 � nsignpres=-1:const%=-const% � nsignpres=+1
�!power_of_2 =�powerof2(const%)
�q� �imop2(const%)<>-1 � work%=-1 :� if can be represented as an immediate constant, no need for work% register
�
�7� �InvReg(outq%) � �InvReg(outr%) � �InvReg(num%) �
�$ � "FastDiv:Invalid Register":�
��
�-� outq%=outr% � outq%=num% � num%=outr% �
�6 �"FastDiv:q,r,num registers Must be different":�
��
�:� outq%=signpres% � outr%=signpres% � num%=signpres% �
> � signpres%<>-1 � �"FastDiv:Invalid signpres register":�
�
@� outq%=work% � outr%=work% � num%=work% � signpres%=work% �
6 � work%<>-1 � �"FastDiv:Invalid work register":�
(�
2
<� const%=1 �
F � nsignpres=+1 �
P [OPT pass%
Z MOV outr%, #0
d MOV outq%, num%
n ]
x �
� [OPT pass%
� MOV outr%, #0
� RSB outq%, num%, #0
� ]
� �
�
=pass%
��
�
�0� set bit31 of this reg to NOT(sign of num%)
� � � �InvReg(signpres%) �
� [OPT pass%
�8 �S signpres%,num%,#&80000000 ; save sign of num
�. RSBNE num%,num%,#0; make num positive
]
�
"%� Carry out Fast Integer Division
, � const%=(1<<power_of_2) �
6 � division by a power of 2
@ [OPT pass%
J% MOV outq%,num%,lsr #power_of_2
T+ SUB outr%,num%,outq%,lsl #power_of_2
^ ]
h�
r
| subflag%=�
�
� � � �InvReg(work%) �
�+ [OPT �megamov(work%, const%, pass%)
� ]
� �
�
� npower_of_2=power_of_2
� const%=const%>>npower_of_2
�
� t1%=1:s%=0:m%=0
� ȕ (t1%<>0) � (m%<=32)
�. � (t1%>=const%) � t1%=t1%-const%:s%+=1
�4 � (t1%<>0) � t1%=(t1%<<1)+1:s%=s%<<1:m%=m%+1
�
t1%=�powerof2(s%)
! power_of_2=power_of_2 - t1%
& s%=s% >> t1%
0 � s%=1 �
:A � MOV outq%,num% (done by joining with next instruction!)
D �
N- [OPT �FastDivAid(outq%,num%,s%,pass%)
X ]
b �
lE ls%=�bitpatlen(s%):� calc:ls (len:s):2^(ls-1)<= s <2^(ls),ls<=m
v7 t1%=m%+1:� generate code for sssss.... to 32 bits
� ȕ t1%<32
� � s%=1 �
� s%=0
� [OPT pass%
�' ADD outq%,num%,num%,LSR #t1%
� ]
� �
� [OPT pass%
�) ADD outq%,outq%,outq%,LSR #t1%
� ]
� �
� t1%=t1%*2
� �
� s%=1 �
4 � Used by some large divisors (eg &7ffffff1)
[OPT pass%
MOV outq%, num%
* ]
4 �
>$ power_of_2=power_of_2+m%-ls%+2
H � power_of_2 <>0 �
R [OPT pass%
\9 MOV outq%,outq%,LSR #power_of_2 ;gen final shift
f ]
p �
zD � const%=1 � �"FastDiv:Sorry Program Error 1, please report":�
�- [OPT �FastMul(outr%,outq%,const%,pass%)
� ]
�" const%=const% << npower_of_2
� � npower_of_2 <>0 �
� [OPT pass%
�/ SUBS outr%,num%,outr%,LSL# npower_of_2
� ]
� �
� [OPT pass%
� SUBS outr%,num%,outr%
� ]
� �
� � �InvReg(work%) �
� subflag% �
[OPT pass%
SUBMI outq%,outq%,#1
$$ ADDMI outr%,outr%,#const%
. ]
8 �
B [OPT pass%
L CMP outr%,#const%
V ADDGE outq%,outq%,#1
`" SUBGE outr%,outr%,#const%
j ]
t �
~ � subflag% �
� [OPT pass%
� SUBMI outq%,outq%,#1
�" ADDMI outr%,outr%,work%
� ]
� �
� [OPT pass%
� CMP outr%,work%
� ADDGE outq%,outq%,#1
� SUBGE outr%,outr%,work%
� ]
� �
��
0� change sign of answer if const%<0 at start
� �InvReg(signpres%) �
� (nsignpres=-1) �
( [OPT pass%
2 RSB outq%,outq%,#0
< ]
F �
P�
Z [OPT pass%
d2 TEQS signpres%,#&80000000 ; get stored sign
nH RSBEQ num%,num%,#0; remove if don't want to preserve original no.
x RSBEQ outr%,outr%,#0
� ]
� � (nsignpres=-1) �
� [OPT pass%
� RSBNE outq%,outq%,#0
� ]
� �
� [OPT pass%
� RSBEQ outq%,outq%,#0
� ]
� �
��
�
�
=pass%
:�Fast Divide Aider:- For Working details see h.FastDiv
�-----------------
"$ݤFastDivAid(Rb,Ra,const%,pass%)
,�
6 � n%,ls%
@� divinst$
JJ� const% = 1 � const%=0:�"FastDivAid:Logic error 1, can't by 1 or 0":�
T5� const%<0 � � 0,"FastDivAid:Logic error 2 found"
^9� Rb=Ra � �"FastDivAid:Registers Must be different":�
hC� �InvReg(Rb) � �InvReg(Ra) � � "FastDivAid:Invalid Register":�
r
|8� Find the length of bit pattern s, from the first 1
�ls%=�bitpatlen(const%)
�
�Ȏ (const% � 3) �
�+� 0,2:� ie sb of form s = s1 * 2^n, n>1
�, � "FastDivAid:Program logic error 3":�
�5� 1: � ie s of form s = s1 * 2^n +1, s1 odd, n>1
� const%-=1
� divinst$="ADD"
�3� 3:� ie s of form s = s1 * 2^n -1, s1 odd, n>1
� const%+=1
� divinst$="SUB"
� subflag%=�
��
'const%=const% >>> �powerof2(const%)
� const%=1 �
� (divinst$="SUB") �
&0 � ls%<=1 � �"FastDivAid:Logic Error 4":�
0 [OPT pass%
:4 ADD Rb,Ra,Ra ;<---FASTDIVaid Gen
D4 SUB Rb,Rb,Ra,LSR#ls% -1 ;<---FASTDIVaid Gen
N ]
X �
b [OPT pass%
l5 ADD Rb,Ra,Ra, LSR #ls%-1 ;<---FASTDIVaid Gen
v ]
� �
��
� � (divinst$="SUB") �
�, [OPT �FastDivAid(Rb,Ra,const%,pass%)
�5 SUB Rb,Rb,Ra, LSR #ls%-1 ;<---FASTDIVaid Gen
� ]
� �
�, [OPT �FastDivAid(Rb,Ra,const%,pass%)
�5 ADD Rb,Rb,Ra, LSR #ls%-1 ;<---FASTDIVaid Gen
� ]
� �
��
�
=pass%
�Fast Multiply
�--------------
* �//initialise macro with
4=�//registers: result ,number to be multiplied by constant
>=�//followed by: the constant you wish to fast multiply by
H0�// generates code to solve to get Rb=Ra * s
R>�//when Ra,Rb are registers and s=constant to multiply by
\F�//if s=0 or s=1 macro aborts !!!! (Try MOV Rb,Ra or MOV Rb,#0 !!)
f.�//Comment: Ra is preserved after the code
pD�//Order of components to use just like a standard instruction !
z
�!ݤFastMul(Rb,Ra,const%,pass%)
�<� Generate instructions for fast multiply Rb=Ra * const%
�� n%
�>� const%=1 � const%=0:�"FastMul:Silly FastMul by 1 or 0":�
�6� Rb=Ra � �"FastMul:Registers Must be different":�
�@� �InvReg(Rb) � �InvReg(Ra) � � "FastMul:Invalid Register":�
�Ȏ (const% � 3) �
�(� 0,2:� const% of form s1 * 2^n, n>1
� n%=�powerof2(const%)
� const%=const%/(1<<n%)
� � const%=1 �
� [OPT pass%
�4 MOV Rb,Ra, LSL #n%;<------FAST MUL generated
]
�
) [OPT �FastMul(Rb,Ra,const%,pass%)
$4 MOV Rb,Rb, LSL #n%;<------FAST MUL generated
. ]
8 �
B1� 1:� const% of form s1 * 2^n +1, s1 odd, n>1
L const%=const%-1
V n%=�powerof2(const%)
` const%=const%/(1<<n%)
j � const%=1 �
t [OPT pass%
~7 ADD Rb,Ra,Ra, LSL #n%;<------FAST MUL generated
� ]
� �
�) [OPT �FastMul(Rb,Ra,const%,pass%)
�7 ADD Rb,Ra,Rb, LSL #n%;<------FAST MUL generated
� ]
� �
�1� 3:� const% of form s1 * 2^n -1, s1 odd, n>1
� const%=const%+1
� n%=�powerof2(const%)
� const%=const%/(1<<n%)
� � const%=1 �
� [OPT pass%
7 RSB Rb,Ra,Ra, LSL #n%;<------FAST MUL generated
]
�
) [OPT �FastMul(Rb,Ra,const%,pass%)
(7 RSB Rb,Ra,Rb, LSL #n%;<------FAST MUL generated
2 ]
< �
F�
P
=pass%
Z
d?� Find length of bit pattern from first 1 to bit 0 position
nݤbitpatlen(S%)
x� Scopy%,ls%
�
Scopy%=S%
� ls%=0
�ȕ Scopy%<>0
� Scopy%=Scopy%>>>1
� ls%+=1
��
�=ls%
�
�
�-� Find highest power of 2 which divides n
�ݤpowerof2(N%)
�� n%
� � N%=0 � =0:� possible error
n%=0
#ȕ (N% � 1)=0:n%+=1:N%=N%>>>1:�
=n%
"
,� Check out registers
6ݤInvReg(reg)
@-=(reg<0 � reg>12) :� Unsensible registers
J
TD� Decompose argument into machine code immediate value operand 2
^"� if possible, else return -1.
hB� IE into an 8 bit chunk 'Imm' & a 4 bit rotation 'Rotate', st
r0� 12 bit operand = Rotate<<8 + Imm,
|@� where original argument = Imm rotated right by (2*Rotate).
�� �imop2(a%)
� � i%, r%
�r%=0
�� i%=0 � 30 � 2
� � (a% � � 255)=0 � = r%�a%
�-a% = (a%>>>30) � (a%<<2) :� ie rot left 2
� r%+= 256
��
�= -1
�
�D� Recall in MOV Rn, #v%, there is a restriction on permitted v%.
�B� Following function assembles a multi-instruction mov capable
� � of taking any 32-bit v%.
B� Aim is to achieve this using as few instructions as possible
?� for each value of v% (never need more than 4, of course).
�
&5� - Well, actually following isn't quite optimal:
0C� It looks for the longest sequence of zero bits, & then splits
:=� rest into 8 bit chunks assigning first using MOV & each
D(� subsequent non-zero one using ORR.
N@� If you were to repeat algo below, but looking for long seq
XD� of 1's instead of zeros, & used a similar process to below to
bD� build mov using MVN & BIC to specify 0's (instead of MOV & ORR
lB� to specify 1's), this would in some cases yield better soln.
v&� So, ideally do both & pick best.
�?� NB That still wouldn't be optimal, but it might be close.
��
�"� Anyone know of a better way?
��
� � �megamov(a%, v%, pass%)
� � i%, m%, r%, mi%, ml%, li%
� � v%=0 �
� [OPT pass%
� MOV a%, #0
� ]
� = pass%
��
�Xr%=0 :� Now need to find the longest span of zeros, allowing bit wrap from b0 to b31
,ȕ (v%�1)=0 :� rotate to get a 1 into b0
v% = (v%>>>31) � (v%<<1)
r%+= 1
�
*i%=0
4m%=1
>0ml%=0 :� Length of longest sequence of zeros
H�
R0 � :� scan till get zero or all bits checked
\ i%+= 1
f m% = m%<<1
p � (i%>31) � ((v%�m%)=0)
z � (i%<32) �
�* li% = i% :� start of a zero sequence
� �
�
i%+= 1
� m% = m%<<1
� � (i%>31) � ((v%�m%)<>0)
�R � (i%-li%)>ml% � mi%=li%:ml%=i%-li% :� start of longest zero sequence so far
� �
� � i%>31
�
� ml%>0 �
�@ � shift to get zero sequence in most significant bits of v%
� i% = 32-(mi%+ml%)
�# v% = (v%>>>(32-i%)) � (v%<<i%)
� r%+= i%
�
� r%�1 �
� r% must be even
$ v% = (v%>>>31) � (v%<<1)
. r%+= 1
8�
B
L � now do the move, at last!
Vi% = v%�255
`[OPT pass%
j7 MOV a%, #(i%>>>r%) � (i%<<(32-r%)) :� ie i% ror r%
t]
~�
� v% = v%>>>8
� � (v%=0) � = pass%
� r% = 31 � (r%-8)
� i% = v%�255
� � i% �
� [OPT pass%
�, �R a%, a%, #(i%>>>r%) � (i%<<(32-r%))
� ]
� �
�� �
� = pass%
�
� �dis(a%, b%)
� q%, w%, q$, i%
� q%=a% � b%-1 � 4
ș &40380, !q%, q% � ,x%,y%
(
q$=""
2 � w%=x% � x%+y%-1
< q$+=�(?w%)
F �
P i% = �q$, ";")
Z
� i%>1 �
d � w%=i%-1 � 1 � -1
n � �q$, w%, 1) <> " " �
x q$ = �q$, w%)
� w%=0
� �
� �
� �
� � q$
��
��
�
�� �nstr(n%)
�� �(n%)<65536 �
� = �(n%)
��
� = "&"+�~(n%)
�
� �err
" � � �
,�:�" with code: ";�/10
6� spool% �
@ *Spool
J
spool%=�
T% �("SetType "+spoolpath$+" Text")
^�
h�
� 00000000 0d 00 0a 11 f4 20 3e 46 41 53 54 44 49 56 62 73 |..... >FASTDIVbs|
00000010 63 0d 00 14 2a f4 20 46 61 73 74 20 44 49 56 2f |c...*. Fast DIV/|
00000020 4d 4f 44 20 20 77 69 74 68 20 61 20 63 6f 6e 73 |MOD with a cons|
00000030 74 61 6e 74 20 6e 75 6d 62 65 72 0d 00 1e 38 f4 |tant number...8.|
00000040 20 63 6f 64 65 20 66 72 61 67 6d 65 6e 74 20 20 | code fragment |
00000050 74 6f 20 74 65 73 74 20 66 61 73 74 64 69 76 2f |to test fastdiv/|
00000060 6d 6f 64 20 63 6f 64 65 20 67 65 6e 65 72 61 74 |mod code generat|
00000070 69 6f 6e 0d 00 28 1f f4 20 41 75 74 68 6f 72 3a |ion..(.. Author:|
00000080 20 53 61 6d 75 65 6c 20 4b 2e 52 2e 20 53 6d 69 | Samuel K.R. Smi|
00000090 74 68 0d 00 32 37 f4 20 48 65 61 76 69 6c 79 20 |th..27. Heavily |
000000a0 4d 4f 44 49 46 49 45 44 20 62 79 20 4d 69 63 68 |MODIFIED by Mich|
000000b0 61 65 6c 20 52 6f 7a 64 6f 62 61 2c 20 46 65 62 |ael Rozdoba, Feb|
000000c0 72 75 61 72 79 20 27 39 35 0d 00 3c 28 f4 20 28 |ruary '95..<(. (|
000000d0 66 69 78 65 73 20 26 20 61 64 64 69 74 69 6f 6e |fixes & addition|
000000e0 61 6c 20 6d 6f 64 69 66 69 63 61 74 69 6f 6e 73 |al modifications|
000000f0 29 0d 00 46 04 0d 00 50 0d ee 85 3a f2 65 72 72 |)..F...P...:.err|
00000100 3a e0 0d 00 5a 07 eb 20 30 0d 00 64 04 0d 00 6e |:...Z.. 0..d...n|
00000110 19 73 70 6f 6f 6c 70 61 74 68 24 20 3d 20 22 46 |.spoolpath$ = "F|
00000120 44 64 65 6d 6f 22 0d 00 78 0c 73 70 6f 6f 6c 25 |Ddemo"..x.spool%|
00000130 3d a3 0d 00 82 23 e7 20 73 70 6f 6f 6c 25 20 ff |=....#. spool% .|
00000140 28 22 53 70 6f 6f 6c 20 22 2b 73 70 6f 6f 6c 70 |("Spool "+spoolp|
00000150 61 74 68 24 29 0d 00 8c 04 0d 00 96 44 f1 20 27 |ath$).......D. '|
00000160 22 46 61 73 74 20 49 6e 74 65 67 65 72 20 44 69 |"Fast Integer Di|
00000170 76 69 73 69 6f 6e 20 43 6f 64 65 20 66 6f 72 20 |vision Code for |
00000180 61 72 62 69 74 72 61 72 79 20 43 4f 4e 53 54 41 |arbitrary CONSTA|
00000190 4e 54 20 44 69 76 69 73 6f 72 20 2d 22 0d 00 a0 |NT Divisor -"...|
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000001b0 26 20 74 65 73 74 69 6e 67 3a 22 27 0d 00 aa 52 |& testing:"'...R|
000001c0 f1 20 22 54 68 69 73 20 70 72 6f 67 72 61 6d 20 |. "This program |
000001d0 6c 69 73 74 73 20 74 68 65 20 64 69 76 69 73 6f |lists the diviso|
000001e0 72 73 20 69 74 20 69 73 20 74 65 73 74 69 6e 67 |rs it is testing|
000001f0 20 26 20 64 69 73 61 73 73 65 6d 62 6c 65 73 20 | & disassembles |
00000200 65 61 63 68 20 72 6f 75 74 69 6e 65 2c 22 0d 00 |each routine,"..|
00000210 b4 4a f1 20 22 65 61 63 68 20 6f 66 20 77 68 69 |.J. "each of whi|
00000220 63 68 20 63 61 6c 63 75 6c 61 74 65 73 20 52 30 |ch calculates R0|
00000230 20 3d 20 52 32 20 44 49 56 20 64 69 76 69 73 6f | = R2 DIV diviso|
00000240 72 2c 20 52 31 20 3d 20 52 32 20 4d 4f 44 20 64 |r, R1 = R2 MOD d|
00000250 69 76 69 73 6f 72 2e 22 0d 00 be 4f f1 20 22 49 |ivisor."...O. "I|
00000260 66 20 69 74 20 66 69 6e 64 73 20 61 6e 20 65 72 |f it finds an er|
00000270 72 6f 72 20 69 74 20 70 72 69 6e 74 73 20 74 68 |ror it prints th|
00000280 65 20 64 65 74 61 69 6c 73 20 61 6e 64 20 77 61 |e details and wa|
00000290 69 74 73 20 66 6f 72 20 61 20 6b 65 79 20 70 72 |its for a key pr|
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000002d0 3d 33 0d 00 e6 04 0d 00 f0 0b 51 25 3d 31 30 30 |=3........Q%=100|
000002e0 30 0d 00 fa 13 52 25 3d 26 37 46 46 46 46 46 46 |0....R%=&7FFFFFF|
000002f0 46 2d 51 25 0d 01 04 13 53 25 3d 26 38 30 30 30 |F-Q%....S%=&8000|
00000300 30 30 30 30 2b 51 25 0d 01 0e 26 6d 61 78 63 25 |0000+Q%...&maxc%|
00000310 3d 30 3a 20 6e 6d 61 78 63 25 3d 30 3a 20 74 6f |=0: nmaxc%=0: to|
00000320 74 63 25 3d 30 3a 20 63 6e 74 25 3d 30 0d 01 18 |tc%=0: cnt%=0...|
00000330 04 0d 01 22 0c 5a 62 61 73 65 25 3d 31 0d 01 2c |...".Zbase%=1..,|
00000340 12 5a 72 61 6e 67 65 25 3d 31 30 30 30 30 30 0d |.Zrange%=100000.|
00000350 01 36 04 0d 01 40 0d 5a 25 3d 5a 62 61 73 65 25 |.6...@.Z%=Zbase%|
00000360 0d 01 4a 05 f5 0d 01 54 1b 20 20 f2 63 68 65 63 |..J....T. .chec|
00000370 6b 28 20 5a 25 2c 2d 51 25 2c 51 25 2c 20 31 29 |k( Z%,-Q%,Q%, 1)|
00000380 0d 01 5e 1b 20 20 f2 63 68 65 63 6b 28 2d 5a 25 |..^. .check(-Z%|
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000003a0 20 f2 63 68 65 63 6b 28 20 5a 25 2c 52 25 2c 26 | .check( Z%,R%,&|
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000003c0 20 20 f2 63 68 65 63 6b 28 2d 5a 25 2c 52 25 2c | .check(-Z%,R%,|
000003d0 26 37 46 46 46 46 46 46 46 2c 20 30 29 0d 01 7c |&7FFFFFFF, 0)..||
000003e0 21 20 20 f2 63 68 65 63 6b 28 20 5a 25 2c 26 38 |! .check( Z%,&8|
000003f0 30 30 30 30 30 30 30 2c 53 25 2c 20 30 29 0d 01 |0000000,S%, 0)..|
00000400 86 21 20 20 f2 63 68 65 63 6b 28 2d 5a 25 2c 26 |.! .check(-Z%,&|
00000410 38 30 30 30 30 30 30 30 2c 53 25 2c 20 30 29 0d |80000000,S%, 0).|
00000420 01 90 1f 20 20 f2 63 68 65 63 6b 28 20 5a 25 2c |... .check( Z%,|
00000430 2d 51 25 2c 51 25 2c 20 31 30 30 2b 30 29 0d 01 |-Q%,Q%, 100+0)..|
00000440 9a 1f 20 20 f2 63 68 65 63 6b 28 2d 5a 25 2c 2d |.. .check(-Z%,-|
00000450 51 25 2c 51 25 2c 20 31 30 30 2d 31 29 0d 01 a4 |Q%,Q%, 100-1)...|
00000460 0f 20 20 63 6e 74 25 20 2b 3d 20 31 0d 01 ae 18 |. cnt% += 1....|
00000470 20 20 6c 25 20 3d 28 61 66 74 25 2d 66 6f 72 65 | l% =(aft%-fore|
00000480 25 29 2f 34 0d 01 b8 11 20 20 74 6f 74 63 25 20 |%)/4.... totc% |
00000490 2b 3d 20 6c 25 0d 01 c2 12 20 20 e7 20 6c 25 3e |+= l%.... . l%>|
000004a0 6d 61 78 63 25 20 8c 0d 01 cc 12 20 20 20 20 6d |maxc% ..... m|
000004b0 61 78 63 25 20 3d 20 6c 25 0d 01 d6 12 20 20 20 |axc% = l%.... |
000004c0 20 6e 6d 61 78 63 25 3d 20 5a 25 0d 01 e0 07 20 | nmaxc%= Z%.... |
000004d0 20 cd 0d 01 ea 52 20 20 f1 22 43 75 72 72 65 6e | ....R ."Curren|
000004e0 74 20 6d 61 78 20 63 6f 64 65 20 6c 65 6e 67 74 |t max code lengt|
000004f0 68 20 22 3b 6d 61 78 63 25 3b 22 20 69 6e 73 74 |h ";maxc%;" inst|
00000500 72 75 63 74 69 6f 6e 73 20 66 6f 72 20 64 69 76 |ructions for div|
00000510 69 73 6f 72 20 22 3b a4 6e 73 74 72 28 6e 6d 61 |isor ";.nstr(nma|
00000520 78 63 25 29 0d 01 f4 3a 20 20 f1 22 41 76 65 72 |xc%)...: ."Aver|
00000530 61 67 65 20 63 6f 64 65 20 6c 65 6e 67 74 68 20 |age code length |
00000540 22 3b 74 6f 74 63 25 2f 63 6e 74 25 3b 22 20 69 |";totc%/cnt%;" i|
00000550 6e 73 74 72 75 63 74 69 6f 6e 73 22 27 27 0d 01 |nstructions"''..|
00000560 fe 09 5a 25 2b 3d 31 0d 02 08 17 fd 20 5a 25 3d |..Z%+=1..... Z%=|
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00001ff0 6c 74 69 70 6c 79 0d 0d 20 13 f4 2d 2d 2d 2d 2d |ltiply.. ..-----|
00002000 2d 2d 2d 2d 2d 2d 2d 2d 2d 0d 0d 2a 1c f4 2f 2f |---------..*..//|
00002010 69 6e 69 74 69 61 6c 69 73 65 20 6d 61 63 72 6f |initialise macro|
00002020 20 77 69 74 68 0d 0d 34 3d f4 2f 2f 72 65 67 69 | with..4=.//regi|
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000020a0 0d 48 30 f4 2f 2f 20 67 65 6e 65 72 61 74 65 73 |.H0.// generates|
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000020d0 0d 52 3e f4 2f 2f 77 68 65 6e 20 52 61 2c 52 62 |.R>.//when Ra,Rb|
000020e0 20 61 72 65 20 72 65 67 69 73 74 65 72 73 20 61 | are registers a|
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00002110 46 f4 2f 2f 69 66 20 73 3d 30 20 6f 72 20 73 3d |F.//if s=0 or s=|
00002120 31 20 6d 61 63 72 6f 20 61 62 6f 72 74 73 20 21 |1 macro aborts !|
00002130 21 21 21 20 28 54 72 79 20 4d 4f 56 20 52 62 2c |!!! (Try MOV Rb,|
00002140 52 61 20 6f 72 20 4d 4f 56 20 52 62 2c 23 30 20 |Ra or MOV Rb,#0 |
00002150 21 21 29 0d 0d 66 2e f4 2f 2f 43 6f 6d 6d 65 6e |!!)..f..//Commen|
00002160 74 3a 20 52 61 20 69 73 20 70 72 65 73 65 72 76 |t: Ra is preserv|
00002170 65 64 20 61 66 74 65 72 20 74 68 65 20 63 6f 64 |ed after the cod|
00002180 65 0d 0d 70 44 f4 2f 2f 4f 72 64 65 72 20 6f 66 |e..pD.//Order of|
00002190 20 63 6f 6d 70 6f 6e 65 6e 74 73 20 74 6f 20 75 | components to u|
000021a0 73 65 20 6a 75 73 74 20 6c 69 6b 65 20 61 20 73 |se just like a s|
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000021c0 69 6f 6e 20 21 0d 0d 7a 04 0d 0d 84 21 dd a4 46 |ion !..z....!..F|
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000021e0 73 74 25 2c 70 61 73 73 25 29 0d 0d 8e 3c f4 20 |st%,pass%)...<. |
000021f0 47 65 6e 65 72 61 74 65 20 69 6e 73 74 72 75 63 |Generate instruc|
00002200 74 69 6f 6e 73 20 66 6f 72 20 66 61 73 74 20 6d |tions for fast m|
00002210 75 6c 74 69 70 6c 79 20 52 62 3d 52 61 20 2a 20 |ultiply Rb=Ra * |
00002220 63 6f 6e 73 74 25 0d 0d 98 08 ea 20 6e 25 0d 0d |const%..... n%..|
00002230 a2 3e e7 20 63 6f 6e 73 74 25 3d 31 20 84 20 63 |.>. const%=1 . c|
00002240 6f 6e 73 74 25 3d 30 3a f1 22 46 61 73 74 4d 75 |onst%=0:."FastMu|
00002250 6c 3a 53 69 6c 6c 79 20 46 61 73 74 4d 75 6c 20 |l:Silly FastMul |
00002260 62 79 20 31 20 6f 72 20 30 22 3a fa 0d 0d ac 36 |by 1 or 0":....6|
00002270 e7 20 52 62 3d 52 61 20 8c 20 f1 22 46 61 73 74 |. Rb=Ra . ."Fast|
00002280 4d 75 6c 3a 52 65 67 69 73 74 65 72 73 20 4d 75 |Mul:Registers Mu|
00002290 73 74 20 62 65 20 64 69 66 66 65 72 65 6e 74 22 |st be different"|
000022a0 3a fa 0d 0d b6 40 e7 20 a4 49 6e 76 52 65 67 28 |:....@. .InvReg(|
000022b0 52 62 29 20 84 20 a4 49 6e 76 52 65 67 28 52 61 |Rb) . .InvReg(Ra|
000022c0 29 20 8c 20 f1 20 22 46 61 73 74 4d 75 6c 3a 49 |) . . "FastMul:I|
000022d0 6e 76 61 6c 69 64 20 52 65 67 69 73 74 65 72 22 |nvalid Register"|
000022e0 3a fa 0d 0d c0 15 c8 8e 20 28 63 6f 6e 73 74 25 |:....... (const%|
000022f0 20 80 20 33 29 20 ca 0d 0d ca 28 c9 20 30 2c 32 | . 3) ....(. 0,2|
00002300 3a f4 20 63 6f 6e 73 74 25 20 6f 66 20 66 6f 72 |:. const% of for|
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00003190 72 25 2b 3d 20 31 0d 13 38 05 cd 0d 13 42 04 0d |r%+= 1..8....B..|
000031a0 13 4c 1f f4 20 6e 6f 77 20 64 6f 20 74 68 65 20 |.L.. now do the |
000031b0 6d 6f 76 65 2c 20 61 74 20 6c 61 73 74 21 0d 13 |move, at last!..|
000031c0 56 0f 69 25 20 3d 20 76 25 80 32 35 35 0d 13 60 |V.i% = v%.255..`|
000031d0 0e 5b 4f 50 54 20 70 61 73 73 25 0d 13 6a 37 20 |.[OPT pass%..j7 |
000031e0 4d 4f 56 20 61 25 2c 20 23 28 69 25 3e 3e 3e 72 |MOV a%, #(i%>>>r|
000031f0 25 29 20 84 20 28 69 25 3c 3c 28 33 32 2d 72 25 |%) . (i%<<(32-r%|
00003200 29 29 20 3a f4 20 69 65 20 69 25 20 72 6f 72 20 |)) :. ie i% ror |
00003210 72 25 0d 13 74 05 5d 0d 13 7e 05 f5 0d 13 88 10 |r%..t.]..~......|
00003220 20 76 25 20 3d 20 76 25 3e 3e 3e 38 0d 13 92 17 | v% = v%>>>8....|
00003230 20 e7 20 28 76 25 3d 30 29 20 8c 20 3d 20 70 61 | . (v%=0) . = pa|
00003240 73 73 25 0d 13 9c 15 20 72 25 20 3d 20 33 31 20 |ss%.... r% = 31 |
00003250 80 20 28 72 25 2d 38 29 0d 13 a6 10 20 69 25 20 |. (r%-8).... i% |
00003260 3d 20 76 25 80 32 35 35 0d 13 b0 0b 20 e7 20 69 |= v%.255.... . i|
00003270 25 20 8c 0d 13 ba 10 20 20 5b 4f 50 54 20 70 61 |% ..... [OPT pa|
00003280 73 73 25 0d 13 c4 2c 20 20 20 84 52 20 61 25 2c |ss%..., .R a%,|
00003290 20 61 25 2c 20 23 28 69 25 3e 3e 3e 72 25 29 20 | a%, #(i%>>>r%) |
000032a0 84 20 28 69 25 3c 3c 28 33 32 2d 72 25 29 29 0d |. (i%<<(32-r%)).|
000032b0 13 ce 07 20 20 5d 0d 13 d8 06 20 cd 0d 13 e2 07 |... ].... .....|
000032c0 fd 20 a3 0d 13 ec 0b 3d 20 70 61 73 73 25 0d 13 |. .....= pass%..|
000032d0 f6 04 0d 14 00 12 dd 20 f2 64 69 73 28 61 25 2c |....... .dis(a%,|
000032e0 20 62 25 29 0d 14 0a 14 ea 20 71 25 2c 20 77 25 | b%)..... q%, w%|
000032f0 2c 20 71 24 2c 20 69 25 0d 14 14 16 e3 20 71 25 |, q$, i%..... q%|
00003300 3d 61 25 20 b8 20 62 25 2d 31 20 88 20 34 0d 14 |=a% . b%-1 . 4..|
00003310 1e 20 20 c8 99 20 26 34 30 33 38 30 2c 20 21 71 |. .. &40380, !q|
00003320 25 2c 20 71 25 20 b8 20 2c 78 25 2c 79 25 0d 14 |%, q% . ,x%,y%..|
00003330 28 0a 20 71 24 3d 22 22 0d 14 32 16 20 e3 20 77 |(. q$=""..2. . w|
00003340 25 3d 78 25 20 b8 20 78 25 2b 79 25 2d 31 0d 14 |%=x% . x%+y%-1..|
00003350 3c 10 20 20 71 24 2b 3d bd 28 3f 77 25 29 0d 14 |<. q$+=.(?w%)..|
00003360 46 06 20 ed 0d 14 50 13 20 69 25 20 3d 20 a7 71 |F. ...P. i% = .q|
00003370 24 2c 20 22 3b 22 29 0d 14 5a 0d 20 e7 20 69 25 |$, ";")..Z. . i%|
00003380 3e 31 20 8c 0d 14 64 18 20 20 e3 20 77 25 3d 69 |>1 ...d. . w%=i|
00003390 25 2d 31 20 b8 20 31 20 88 20 2d 31 0d 14 6e 1d |%-1 . 1 . -1..n.|
000033a0 20 20 20 e7 20 c1 71 24 2c 20 77 25 2c 20 31 29 | . .q$, w%, 1)|
000033b0 20 3c 3e 20 22 20 22 20 8c 0d 14 78 15 20 20 20 | <> " " ...x. |
000033c0 20 71 24 20 3d 20 c0 71 24 2c 20 77 25 29 0d 14 | q$ = .q$, w%)..|
000033d0 82 0c 20 20 20 20 77 25 3d 30 0d 14 8c 08 20 20 |.. w%=0.... |
000033e0 20 cd 0d 14 96 07 20 20 ed 0d 14 a0 06 20 cd 0d | ..... ..... ..|
000033f0 14 aa 09 20 f1 20 71 24 0d 14 b4 05 ed 0d 14 be |... . q$........|
00003400 05 e1 0d 14 c8 04 0d 14 d2 0f dd 20 a4 6e 73 74 |........... .nst|
00003410 72 28 6e 25 29 0d 14 dc 13 e7 20 94 28 6e 25 29 |r(n%)..... .(n%)|
00003420 3c 36 35 35 33 36 20 8c 0d 14 e6 0c 20 3d 20 c3 |<65536 ..... = .|
00003430 28 6e 25 29 0d 14 f0 05 cc 0d 14 fa 11 20 3d 20 |(n%)......... = |
00003440 22 26 22 2b c3 7e 28 6e 25 29 0d 15 04 05 cd 0d |"&"+.~(n%)......|
00003450 15 0e 04 0d 15 18 0a dd 20 f2 65 72 72 0d 15 22 |........ .err.."|
00003460 09 ee 20 85 20 87 0d 15 2c 1a f6 3a f1 22 20 77 |.. . ...,..:." w|
00003470 69 74 68 20 63 6f 64 65 3a 20 22 3b 9e 2f 31 30 |ith code: ";./10|
00003480 0d 15 36 0e e7 20 73 70 6f 6f 6c 25 20 8c 0d 15 |..6.. spool% ...|
00003490 40 0b 20 2a 53 70 6f 6f 6c 0d 15 4a 0d 20 73 70 |@. *Spool..J. sp|
000034a0 6f 6f 6c 25 3d a3 0d 15 54 25 20 ff 28 22 53 65 |ool%=...T% .("Se|
000034b0 74 54 79 70 65 20 22 2b 73 70 6f 6f 6c 70 61 74 |tType "+spoolpat|
000034c0 68 24 2b 22 20 54 65 78 74 22 29 0d 15 5e 05 cd |h$+" Text")..^..|
000034d0 0d 15 68 05 e1 0d ff |..h....|
000034d7 
.