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F/+HINT6
This website contains an archive of files for the Acorn Electron, BBC Micro, Acorn Archimedes, Commodore 16 and Commodore 64 computers, which Dominic Ford has rescued from his private collection of floppy disks and cassettes.
Some of these files were originally commercial releases in the 1980s and 1990s, but they are now widely available online. I assume that copyright over them is no longer being asserted. If you own the copyright and would like files to be removed, please contact me.
| Tape/disk: | Home » Personal collection » Acorn ADFS disks » Electron_User_Group » EUG_30.ADF |
| Filename: | F/+HINT6 |
| Read OK: | ✔ |
| File size: | 11A0 bytes |
| Load address: | 2B204556 |
| Exec address: | 544E4948 |
File contents
4.0 Timing
Processor Clock:
The Electron clock changes speed depending on what is being accessed at
the time.
During accesses to the ROM the processor runs at 2MHz; PHI OUT is low for
250ns followed by high for 250ns (nominal).
During access to I/O and to RAM in modes 4-6 the processor runs at 1 MHz.
The transition from 2Mhz to 1MHz is accomplished by having PHI OUT low
time of 250ns followed by a high time of either 750 or 1250ns depending on
the phase of the 2MHz signal, see Figure 2. The reason for this is that
the processor will re-synchronise to the 1Mhz clock, making interfacing to
peripherals such as the 6522 possible. The 1MHz clock is not available
outside the ULA; it must be generated externally.
(Fig.2)
In modes 0-3 the processor is denied access to the RAM during the
displayed portion of the screen (40us out of 64us in 256 lines out of
312). If the processor requires access to the RAM during this time it is
forced to wait until the end of the 40us line display period. ROM access
during this time is allowed. The effect of all this is that the processor
clock may be stretched in the high state for a period of up to 40us.
4.1 Regeneration of PHI
The timing of signal supplied to the Electron expansion are 16MHz, PHI OUT
(the processor input clock), and 16M/13 (for baud rate generation).
Signals such as 1MHz and 2MHz are used inside the ULA but do not exist
outside. Since, for example, the 6522 needs a 1MHz clock in phase with
the processor clock, this must be generated externally, see Figure 3.
4.2 Interrupt Latency
The longest period for which interrupts (IRQs) are disabled determines the
frequency at which new interrupts can be serviced. When the Electron is
in modes 0-3 this period (known as interrupt latency) can be as long as
10ms worst case. This can cause problems for RS423, A/D conversion, etc.
In modes 4-6 the interrupt latency is 4ms worst case, so actions which
require fast access or high data rate must force the Electron into one of
these modes.
Use of an ACIA or UART with FIFO capability and/or a handshake will
increase data throughput.
5.0 Sideways ROMs
Decoding:
Decoding of sideways ROMs is carried out at location &FE05. Any expansion
module which uses sideways ROMs must include circuitry to intercept the
write to &FE05 and act appropriately. The ULA handles the keyboard (ROM
numbers 8 and 9) and BASIC (ROM numbers 10 and 11). These four ROM
numbers are decoded inside the Electron itself and are not available for
use by an expansion module. All other ROM calls must be decoded by the
expansion module at address &FE05.
Twelve sideways ROMs can be accommodated on the Electron expansion, and
four (ROM numbers 12 to 15) are accessible by a single write to &FE05.
D7 D6 D5 D4 D3 D2 D1 D0
Write at &FE05 0 0 0 0 1 1 R1 R0
Where R1 R0 selects which of the four ROMs is required. These four ROMs
are numbered 12 to 15.
Selection of a ROM number 12 to 13 will take the following form:
LDA# ROMnumber
STA &F4
STA &Fe05
The write to &F4 must be carried out before the write to &FE05 in case an
interrupt occurs. The write to &FE05 tells the ULA that a sideways ROM is
to be accessed and it passes control to the operating system. Hardware in
the expansion module must decode the write to &FE05 and select one of the
four ROMs.
Now that BASIC has been de-selected, a further write to &FE05 can be
decoded by the expansion module to select ROMs numbered from 0 to 7.
D7 D6 D5 D4 D3 D2 D1 D0
Write at &FE05 0 0 0 0 0 R2 R1 R0
where R2 R1 R0 select which of the eight ROMs is required. These eight
ROMs are numbered 0 to 7.
Once again, the write to &FE05 must be decoded by hardware in the
expansion module which selects one of the eight ROMs.
Selection of a ROM number 0 to 7 will take the following form:
LDA# &0C \to
STA &F4 \deselect
STA &FE05 \BASIC
LDA# ROMnumber
STA &F4
STA &FE05
On power-up, sideways ROMs are polled in the order 15 through to 0 to find
the first which is configured as a language ROM. Execution will then
commence in this ROM. As BASIC is ROM number 10/11, a ROM in an expansion
module which is required to power-up before BASIC must be numbered 12 to
15.
00000000 0d 34 2e 30 20 20 54 69 6d 69 6e 67 0d 0d 50 72 |.4.0 Timing..Pr| 00000010 6f 63 65 73 73 6f 72 20 43 6c 6f 63 6b 3a 0d 0d |ocessor Clock:..| 00000020 54 68 65 20 45 6c 65 63 74 72 6f 6e 20 63 6c 6f |The Electron clo| 00000030 63 6b 20 63 68 61 6e 67 65 73 20 73 70 65 65 64 |ck changes speed| 00000040 20 64 65 70 65 6e 64 69 6e 67 20 6f 6e 20 77 68 | depending on wh| 00000050 61 74 20 69 73 20 62 65 69 6e 67 20 61 63 63 65 |at is being acce| 00000060 73 73 65 64 20 61 74 0d 74 68 65 20 74 69 6d 65 |ssed at.the time| 00000070 2e 0d 0d 44 75 72 69 6e 67 20 61 63 63 65 73 73 |...During access| 00000080 65 73 20 74 6f 20 74 68 65 20 52 4f 4d 20 74 68 |es to the ROM th| 00000090 65 20 70 72 6f 63 65 73 73 6f 72 20 72 75 6e 73 |e processor runs| 000000a0 20 61 74 20 32 4d 48 7a 3b 20 50 48 49 20 4f 55 | at 2MHz; PHI OU| 000000b0 54 20 69 73 20 6c 6f 77 20 66 6f 72 0d 32 35 30 |T is low for.250| 000000c0 6e 73 20 66 6f 6c 6c 6f 77 65 64 20 62 79 20 68 |ns followed by h| 000000d0 69 67 68 20 66 6f 72 20 32 35 30 6e 73 20 28 6e |igh for 250ns (n| 000000e0 6f 6d 69 6e 61 6c 29 2e 0d 0d 44 75 72 69 6e 67 |ominal)...During| 000000f0 20 61 63 63 65 73 73 20 74 6f 20 49 2f 4f 20 61 | access to I/O a| 00000100 6e 64 20 74 6f 20 52 41 4d 20 69 6e 20 6d 6f 64 |nd to RAM in mod| 00000110 65 73 20 34 2d 36 20 74 68 65 20 70 72 6f 63 65 |es 4-6 the proce| 00000120 73 73 6f 72 20 72 75 6e 73 20 61 74 20 31 20 4d |ssor runs at 1 M| 00000130 48 7a 2e 20 0d 54 68 65 20 74 72 61 6e 73 69 74 |Hz. .The transit| 00000140 69 6f 6e 20 66 72 6f 6d 20 32 4d 68 7a 20 74 6f |ion from 2Mhz to| 00000150 20 31 4d 48 7a 20 69 73 20 61 63 63 6f 6d 70 6c | 1MHz is accompl| 00000160 69 73 68 65 64 20 62 79 20 68 61 76 69 6e 67 20 |ished by having | 00000170 50 48 49 20 4f 55 54 20 6c 6f 77 0d 74 69 6d 65 |PHI OUT low.time| 00000180 20 6f 66 20 32 35 30 6e 73 20 66 6f 6c 6c 6f 77 | of 250ns follow| 00000190 65 64 20 62 79 20 61 20 68 69 67 68 20 74 69 6d |ed by a high tim| 000001a0 65 20 6f 66 20 65 69 74 68 65 72 20 37 35 30 20 |e of either 750 | 000001b0 6f 72 20 31 32 35 30 6e 73 20 64 65 70 65 6e 64 |or 1250ns depend| 000001c0 69 6e 67 20 6f 6e 0d 74 68 65 20 70 68 61 73 65 |ing on.the phase| 000001d0 20 6f 66 20 74 68 65 20 32 4d 48 7a 20 73 69 67 | of the 2MHz sig| 000001e0 6e 61 6c 2c 20 73 65 65 20 46 69 67 75 72 65 20 |nal, see Figure | 000001f0 32 2e 20 20 54 68 65 20 72 65 61 73 6f 6e 20 66 |2. The reason f| 00000200 6f 72 20 74 68 69 73 20 69 73 20 74 68 61 74 0d |or this is that.| 00000210 74 68 65 20 70 72 6f 63 65 73 73 6f 72 20 77 69 |the processor wi| 00000220 6c 6c 20 72 65 2d 73 79 6e 63 68 72 6f 6e 69 73 |ll re-synchronis| 00000230 65 20 74 6f 20 74 68 65 20 31 4d 68 7a 20 63 6c |e to the 1Mhz cl| 00000240 6f 63 6b 2c 20 6d 61 6b 69 6e 67 20 69 6e 74 65 |ock, making inte| 00000250 72 66 61 63 69 6e 67 20 74 6f 0d 70 65 72 69 70 |rfacing to.perip| 00000260 68 65 72 61 6c 73 20 73 75 63 68 20 61 73 20 74 |herals such as t| 00000270 68 65 20 36 35 32 32 20 70 6f 73 73 69 62 6c 65 |he 6522 possible| 00000280 2e 20 20 54 68 65 20 31 4d 48 7a 20 63 6c 6f 63 |. The 1MHz cloc| 00000290 6b 20 69 73 20 6e 6f 74 20 61 76 61 69 6c 61 62 |k is not availab| 000002a0 6c 65 0d 6f 75 74 73 69 64 65 20 74 68 65 20 55 |le.outside the U| 000002b0 4c 41 3b 20 69 74 20 6d 75 73 74 20 62 65 20 67 |LA; it must be g| 000002c0 65 6e 65 72 61 74 65 64 20 65 78 74 65 72 6e 61 |enerated externa| 000002d0 6c 6c 79 2e 0d 0d 28 46 69 67 2e 32 29 0d 0d 49 |lly...(Fig.2)..I| 000002e0 6e 20 6d 6f 64 65 73 20 30 2d 33 20 74 68 65 20 |n modes 0-3 the | 000002f0 70 72 6f 63 65 73 73 6f 72 20 69 73 20 64 65 6e |processor is den| 00000300 69 65 64 20 61 63 63 65 73 73 20 74 6f 20 74 68 |ied access to th| 00000310 65 20 52 41 4d 20 64 75 72 69 6e 67 20 74 68 65 |e RAM during the| 00000320 0d 64 69 73 70 6c 61 79 65 64 20 70 6f 72 74 69 |.displayed porti| 00000330 6f 6e 20 6f 66 20 74 68 65 20 73 63 72 65 65 6e |on of the screen| 00000340 20 28 34 30 75 73 20 6f 75 74 20 6f 66 20 36 34 | (40us out of 64| 00000350 75 73 20 69 6e 20 32 35 36 20 6c 69 6e 65 73 20 |us in 256 lines | 00000360 6f 75 74 20 6f 66 0d 33 31 32 29 2e 20 20 49 66 |out of.312). If| 00000370 20 74 68 65 20 70 72 6f 63 65 73 73 6f 72 20 72 | the processor r| 00000380 65 71 75 69 72 65 73 20 61 63 63 65 73 73 20 74 |equires access t| 00000390 6f 20 74 68 65 20 52 41 4d 20 64 75 72 69 6e 67 |o the RAM during| 000003a0 20 74 68 69 73 20 74 69 6d 65 20 69 74 20 69 73 | this time it is| 000003b0 0d 66 6f 72 63 65 64 20 74 6f 20 77 61 69 74 20 |.forced to wait | 000003c0 75 6e 74 69 6c 20 74 68 65 20 65 6e 64 20 6f 66 |until the end of| 000003d0 20 74 68 65 20 34 30 75 73 20 6c 69 6e 65 20 64 | the 40us line d| 000003e0 69 73 70 6c 61 79 20 70 65 72 69 6f 64 2e 20 20 |isplay period. | 000003f0 52 4f 4d 20 61 63 63 65 73 73 0d 64 75 72 69 6e |ROM access.durin| 00000400 67 20 74 68 69 73 20 74 69 6d 65 20 69 73 20 61 |g this time is a| 00000410 6c 6c 6f 77 65 64 2e 20 20 54 68 65 20 65 66 66 |llowed. The eff| 00000420 65 63 74 20 6f 66 20 61 6c 6c 20 74 68 69 73 20 |ect of all this | 00000430 69 73 20 74 68 61 74 20 74 68 65 20 70 72 6f 63 |is that the proc| 00000440 65 73 73 6f 72 0d 63 6c 6f 63 6b 20 6d 61 79 20 |essor.clock may | 00000450 62 65 20 73 74 72 65 74 63 68 65 64 20 69 6e 20 |be stretched in | 00000460 74 68 65 20 68 69 67 68 20 73 74 61 74 65 20 66 |the high state f| 00000470 6f 72 20 61 20 70 65 72 69 6f 64 20 6f 66 20 75 |or a period of u| 00000480 70 20 74 6f 20 34 30 75 73 2e 0d 0d 0d 34 2e 31 |p to 40us....4.1| 00000490 20 20 52 65 67 65 6e 65 72 61 74 69 6f 6e 20 6f | Regeneration o| 000004a0 66 20 50 48 49 0d 0d 54 68 65 20 74 69 6d 69 6e |f PHI..The timin| 000004b0 67 20 6f 66 20 73 69 67 6e 61 6c 20 73 75 70 70 |g of signal supp| 000004c0 6c 69 65 64 20 74 6f 20 74 68 65 20 45 6c 65 63 |lied to the Elec| 000004d0 74 72 6f 6e 20 65 78 70 61 6e 73 69 6f 6e 20 61 |tron expansion a| 000004e0 72 65 20 31 36 4d 48 7a 2c 20 50 48 49 20 4f 55 |re 16MHz, PHI OU| 000004f0 54 0d 28 74 68 65 20 70 72 6f 63 65 73 73 6f 72 |T.(the processor| 00000500 20 69 6e 70 75 74 20 63 6c 6f 63 6b 29 2c 20 61 | input clock), a| 00000510 6e 64 20 31 36 4d 2f 31 33 20 28 66 6f 72 20 62 |nd 16M/13 (for b| 00000520 61 75 64 20 72 61 74 65 20 67 65 6e 65 72 61 74 |aud rate generat| 00000530 69 6f 6e 29 2e 20 0d 53 69 67 6e 61 6c 73 20 73 |ion). .Signals s| 00000540 75 63 68 20 61 73 20 31 4d 48 7a 20 61 6e 64 20 |uch as 1MHz and | 00000550 32 4d 48 7a 20 61 72 65 20 75 73 65 64 20 69 6e |2MHz are used in| 00000560 73 69 64 65 20 74 68 65 20 55 4c 41 20 62 75 74 |side the ULA but| 00000570 20 64 6f 20 6e 6f 74 20 65 78 69 73 74 0d 6f 75 | do not exist.ou| 00000580 74 73 69 64 65 2e 20 20 53 69 6e 63 65 2c 20 66 |tside. Since, f| 00000590 6f 72 20 65 78 61 6d 70 6c 65 2c 20 74 68 65 20 |or example, the | 000005a0 36 35 32 32 20 6e 65 65 64 73 20 61 20 31 4d 48 |6522 needs a 1MH| 000005b0 7a 20 63 6c 6f 63 6b 20 69 6e 20 70 68 61 73 65 |z clock in phase| 000005c0 20 77 69 74 68 0d 74 68 65 20 70 72 6f 63 65 73 | with.the proces| 000005d0 73 6f 72 20 63 6c 6f 63 6b 2c 20 74 68 69 73 20 |sor clock, this | 000005e0 6d 75 73 74 20 62 65 20 67 65 6e 65 72 61 74 65 |must be generate| 000005f0 64 20 65 78 74 65 72 6e 61 6c 6c 79 2c 20 73 65 |d externally, se| 00000600 65 20 46 69 67 75 72 65 20 33 2e 0d 0d 0d 34 2e |e Figure 3....4.| 00000610 32 20 20 49 6e 74 65 72 72 75 70 74 20 4c 61 74 |2 Interrupt Lat| 00000620 65 6e 63 79 0d 0d 54 68 65 20 6c 6f 6e 67 65 73 |ency..The longes| 00000630 74 20 70 65 72 69 6f 64 20 66 6f 72 20 77 68 69 |t period for whi| 00000640 63 68 20 69 6e 74 65 72 72 75 70 74 73 20 28 49 |ch interrupts (I| 00000650 52 51 73 29 20 61 72 65 20 64 69 73 61 62 6c 65 |RQs) are disable| 00000660 64 20 64 65 74 65 72 6d 69 6e 65 73 20 74 68 65 |d determines the| 00000670 0d 66 72 65 71 75 65 6e 63 79 20 61 74 20 77 68 |.frequency at wh| 00000680 69 63 68 20 6e 65 77 20 69 6e 74 65 72 72 75 70 |ich new interrup| 00000690 74 73 20 63 61 6e 20 62 65 20 73 65 72 76 69 63 |ts can be servic| 000006a0 65 64 2e 20 20 57 68 65 6e 20 74 68 65 20 45 6c |ed. When the El| 000006b0 65 63 74 72 6f 6e 20 69 73 0d 69 6e 20 6d 6f 64 |ectron is.in mod| 000006c0 65 73 20 30 2d 33 20 74 68 69 73 20 70 65 72 69 |es 0-3 this peri| 000006d0 6f 64 20 28 6b 6e 6f 77 6e 20 61 73 20 69 6e 74 |od (known as int| 000006e0 65 72 72 75 70 74 20 6c 61 74 65 6e 63 79 29 20 |errupt latency) | 000006f0 63 61 6e 20 62 65 20 61 73 20 6c 6f 6e 67 20 61 |can be as long a| 00000700 73 0d 31 30 6d 73 20 77 6f 72 73 74 20 63 61 73 |s.10ms worst cas| 00000710 65 2e 20 20 54 68 69 73 20 63 61 6e 20 63 61 75 |e. This can cau| 00000720 73 65 20 70 72 6f 62 6c 65 6d 73 20 66 6f 72 20 |se problems for | 00000730 52 53 34 32 33 2c 20 41 2f 44 20 63 6f 6e 76 65 |RS423, A/D conve| 00000740 72 73 69 6f 6e 2c 20 65 74 63 2e 0d 0d 49 6e 20 |rsion, etc...In | 00000750 6d 6f 64 65 73 20 34 2d 36 20 74 68 65 20 69 6e |modes 4-6 the in| 00000760 74 65 72 72 75 70 74 20 6c 61 74 65 6e 63 79 20 |terrupt latency | 00000770 69 73 20 34 6d 73 20 77 6f 72 73 74 20 63 61 73 |is 4ms worst cas| 00000780 65 2c 20 73 6f 20 61 63 74 69 6f 6e 73 20 77 68 |e, so actions wh| 00000790 69 63 68 0d 72 65 71 75 69 72 65 20 66 61 73 74 |ich.require fast| 000007a0 20 61 63 63 65 73 73 20 6f 72 20 68 69 67 68 20 | access or high | 000007b0 64 61 74 61 20 72 61 74 65 20 6d 75 73 74 20 66 |data rate must f| 000007c0 6f 72 63 65 20 74 68 65 20 45 6c 65 63 74 72 6f |orce the Electro| 000007d0 6e 20 69 6e 74 6f 20 6f 6e 65 20 6f 66 0d 74 68 |n into one of.th| 000007e0 65 73 65 20 6d 6f 64 65 73 2e 0d 0d 55 73 65 20 |ese modes...Use | 000007f0 6f 66 20 61 6e 20 41 43 49 41 20 6f 72 20 55 41 |of an ACIA or UA| 00000800 52 54 20 77 69 74 68 20 46 49 46 4f 20 63 61 70 |RT with FIFO cap| 00000810 61 62 69 6c 69 74 79 20 61 6e 64 2f 6f 72 20 61 |ability and/or a| 00000820 20 68 61 6e 64 73 68 61 6b 65 20 77 69 6c 6c 0d | handshake will.| 00000830 69 6e 63 72 65 61 73 65 20 64 61 74 61 20 74 68 |increase data th| 00000840 72 6f 75 67 68 70 75 74 2e 0d 0d 0d 35 2e 30 20 |roughput....5.0 | 00000850 20 53 69 64 65 77 61 79 73 20 52 4f 4d 73 0d 0d | Sideways ROMs..| 00000860 44 65 63 6f 64 69 6e 67 3a 0d 0d 44 65 63 6f 64 |Decoding:..Decod| 00000870 69 6e 67 20 6f 66 20 73 69 64 65 77 61 79 73 20 |ing of sideways | 00000880 52 4f 4d 73 20 69 73 20 63 61 72 72 69 65 64 20 |ROMs is carried | 00000890 6f 75 74 20 61 74 20 6c 6f 63 61 74 69 6f 6e 20 |out at location | 000008a0 26 46 45 30 35 2e 20 20 41 6e 79 20 65 78 70 61 |&FE05. Any expa| 000008b0 6e 73 69 6f 6e 0d 6d 6f 64 75 6c 65 20 77 68 69 |nsion.module whi| 000008c0 63 68 20 75 73 65 73 20 73 69 64 65 77 61 79 73 |ch uses sideways| 000008d0 20 52 4f 4d 73 20 6d 75 73 74 20 69 6e 63 6c 75 | ROMs must inclu| 000008e0 64 65 20 63 69 72 63 75 69 74 72 79 20 74 6f 20 |de circuitry to | 000008f0 69 6e 74 65 72 63 65 70 74 20 74 68 65 0d 77 72 |intercept the.wr| 00000900 69 74 65 20 74 6f 20 26 46 45 30 35 20 61 6e 64 |ite to &FE05 and| 00000910 20 61 63 74 20 61 70 70 72 6f 70 72 69 61 74 65 | act appropriate| 00000920 6c 79 2e 20 20 54 68 65 20 55 4c 41 20 68 61 6e |ly. The ULA han| 00000930 64 6c 65 73 20 74 68 65 20 6b 65 79 62 6f 61 72 |dles the keyboar| 00000940 64 20 28 52 4f 4d 0d 6e 75 6d 62 65 72 73 20 38 |d (ROM.numbers 8| 00000950 20 61 6e 64 20 39 29 20 61 6e 64 20 42 41 53 49 | and 9) and BASI| 00000960 43 20 28 52 4f 4d 20 6e 75 6d 62 65 72 73 20 31 |C (ROM numbers 1| 00000970 30 20 61 6e 64 20 31 31 29 2e 20 20 54 68 65 73 |0 and 11). Thes| 00000980 65 20 66 6f 75 72 20 52 4f 4d 0d 6e 75 6d 62 65 |e four ROM.numbe| 00000990 72 73 20 61 72 65 20 64 65 63 6f 64 65 64 20 69 |rs are decoded i| 000009a0 6e 73 69 64 65 20 74 68 65 20 45 6c 65 63 74 72 |nside the Electr| 000009b0 6f 6e 20 69 74 73 65 6c 66 20 61 6e 64 20 61 72 |on itself and ar| 000009c0 65 20 6e 6f 74 20 61 76 61 69 6c 61 62 6c 65 20 |e not available | 000009d0 66 6f 72 0d 75 73 65 20 62 79 20 61 6e 20 65 78 |for.use by an ex| 000009e0 70 61 6e 73 69 6f 6e 20 6d 6f 64 75 6c 65 2e 20 |pansion module. | 000009f0 20 41 6c 6c 20 6f 74 68 65 72 20 52 4f 4d 20 63 | All other ROM c| 00000a00 61 6c 6c 73 20 6d 75 73 74 20 62 65 20 64 65 63 |alls must be dec| 00000a10 6f 64 65 64 20 62 79 20 74 68 65 0d 65 78 70 61 |oded by the.expa| 00000a20 6e 73 69 6f 6e 20 6d 6f 64 75 6c 65 20 61 74 20 |nsion module at | 00000a30 61 64 64 72 65 73 73 20 26 46 45 30 35 2e 0d 0d |address &FE05...| 00000a40 54 77 65 6c 76 65 20 73 69 64 65 77 61 79 73 20 |Twelve sideways | 00000a50 52 4f 4d 73 20 63 61 6e 20 62 65 20 61 63 63 6f |ROMs can be acco| 00000a60 6d 6d 6f 64 61 74 65 64 20 6f 6e 20 74 68 65 20 |mmodated on the | 00000a70 45 6c 65 63 74 72 6f 6e 20 65 78 70 61 6e 73 69 |Electron expansi| 00000a80 6f 6e 2c 20 61 6e 64 0d 66 6f 75 72 20 28 52 4f |on, and.four (RO| 00000a90 4d 20 6e 75 6d 62 65 72 73 20 31 32 20 74 6f 20 |M numbers 12 to | 00000aa0 31 35 29 20 61 72 65 20 61 63 63 65 73 73 69 62 |15) are accessib| 00000ab0 6c 65 20 62 79 20 61 20 73 69 6e 67 6c 65 20 77 |le by a single w| 00000ac0 72 69 74 65 20 74 6f 20 26 46 45 30 35 2e 0d 0d |rite to &FE05...| 00000ad0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | | 00000ae0 44 37 20 20 20 20 20 20 44 36 20 20 20 20 20 20 |D7 D6 | 00000af0 44 35 20 20 20 20 20 20 44 34 20 20 20 20 20 20 |D5 D4 | 00000b00 44 33 20 20 20 20 20 20 44 32 20 20 20 20 20 20 |D3 D2 | 00000b10 44 31 20 20 20 20 20 20 44 30 0d 57 72 69 74 65 |D1 D0.Write| 00000b20 20 61 74 20 26 46 45 30 35 20 20 30 20 20 20 20 | at &FE05 0 | 00000b30 20 20 20 30 20 20 20 20 20 20 20 30 20 20 20 20 | 0 0 | 00000b40 20 20 20 30 20 20 20 20 20 20 20 31 20 20 20 20 | 0 1 | 00000b50 20 20 20 31 20 20 20 20 20 20 20 52 31 20 20 20 | 1 R1 | 00000b60 20 20 20 52 30 0d 0d 57 68 65 72 65 20 52 31 20 | R0..Where R1 | 00000b70 52 30 20 73 65 6c 65 63 74 73 20 77 68 69 63 68 |R0 selects which| 00000b80 20 6f 66 20 74 68 65 20 66 6f 75 72 20 52 4f 4d | of the four ROM| 00000b90 73 20 69 73 20 72 65 71 75 69 72 65 64 2e 20 20 |s is required. | 00000ba0 54 68 65 73 65 20 66 6f 75 72 20 52 4f 4d 73 0d |These four ROMs.| 00000bb0 61 72 65 20 6e 75 6d 62 65 72 65 64 20 31 32 20 |are numbered 12 | 00000bc0 74 6f 20 31 35 2e 0d 0d 53 65 6c 65 63 74 69 6f |to 15...Selectio| 00000bd0 6e 20 6f 66 20 61 20 52 4f 4d 20 6e 75 6d 62 65 |n of a ROM numbe| 00000be0 72 20 31 32 20 74 6f 20 31 33 20 77 69 6c 6c 20 |r 12 to 13 will | 00000bf0 74 61 6b 65 20 74 68 65 20 66 6f 6c 6c 6f 77 69 |take the followi| 00000c00 6e 67 20 66 6f 72 6d 3a 0d 0d 20 20 20 20 20 20 |ng form:.. | 00000c10 20 20 4c 44 41 23 20 20 20 52 4f 4d 6e 75 6d 62 | LDA# ROMnumb| 00000c20 65 72 0d 20 20 20 20 20 20 20 20 53 54 41 20 20 |er. STA | 00000c30 20 20 20 20 26 46 34 0d 20 20 20 20 20 20 20 20 | &F4. | 00000c40 53 54 41 20 20 20 20 20 20 26 46 65 30 35 0d 0d |STA &Fe05..| 00000c50 54 68 65 20 77 72 69 74 65 20 74 6f 20 26 46 34 |The write to &F4| 00000c60 20 6d 75 73 74 20 62 65 20 63 61 72 72 69 65 64 | must be carried| 00000c70 20 6f 75 74 20 62 65 66 6f 72 65 20 74 68 65 20 | out before the | 00000c80 77 72 69 74 65 20 74 6f 20 26 46 45 30 35 20 69 |write to &FE05 i| 00000c90 6e 20 63 61 73 65 20 61 6e 0d 69 6e 74 65 72 72 |n case an.interr| 00000ca0 75 70 74 20 6f 63 63 75 72 73 2e 20 20 54 68 65 |upt occurs. The| 00000cb0 20 77 72 69 74 65 20 74 6f 20 26 46 45 30 35 20 | write to &FE05 | 00000cc0 74 65 6c 6c 73 20 74 68 65 20 55 4c 41 20 74 68 |tells the ULA th| 00000cd0 61 74 20 61 20 73 69 64 65 77 61 79 73 20 52 4f |at a sideways RO| 00000ce0 4d 20 69 73 0d 74 6f 20 62 65 20 61 63 63 65 73 |M is.to be acces| 00000cf0 73 65 64 20 61 6e 64 20 69 74 20 70 61 73 73 65 |sed and it passe| 00000d00 73 20 63 6f 6e 74 72 6f 6c 20 74 6f 20 74 68 65 |s control to the| 00000d10 20 6f 70 65 72 61 74 69 6e 67 20 73 79 73 74 65 | operating syste| 00000d20 6d 2e 20 20 48 61 72 64 77 61 72 65 20 69 6e 0d |m. Hardware in.| 00000d30 74 68 65 20 65 78 70 61 6e 73 69 6f 6e 20 6d 6f |the expansion mo| 00000d40 64 75 6c 65 20 6d 75 73 74 20 64 65 63 6f 64 65 |dule must decode| 00000d50 20 74 68 65 20 77 72 69 74 65 20 74 6f 20 26 46 | the write to &F| 00000d60 45 30 35 20 61 6e 64 20 73 65 6c 65 63 74 20 6f |E05 and select o| 00000d70 6e 65 20 6f 66 20 74 68 65 0d 66 6f 75 72 20 52 |ne of the.four R| 00000d80 4f 4d 73 2e 0d 0d 4e 6f 77 20 74 68 61 74 20 42 |OMs...Now that B| 00000d90 41 53 49 43 20 68 61 73 20 62 65 65 6e 20 64 65 |ASIC has been de| 00000da0 2d 73 65 6c 65 63 74 65 64 2c 20 61 20 66 75 72 |-selected, a fur| 00000db0 74 68 65 72 20 77 72 69 74 65 20 74 6f 20 26 46 |ther write to &F| 00000dc0 45 30 35 20 63 61 6e 20 62 65 0d 64 65 63 6f 64 |E05 can be.decod| 00000dd0 65 64 20 62 79 20 74 68 65 20 65 78 70 61 6e 73 |ed by the expans| 00000de0 69 6f 6e 20 6d 6f 64 75 6c 65 20 74 6f 20 73 65 |ion module to se| 00000df0 6c 65 63 74 20 52 4f 4d 73 20 6e 75 6d 62 65 72 |lect ROMs number| 00000e00 65 64 20 66 72 6f 6d 20 30 20 74 6f 20 37 2e 20 |ed from 0 to 7. | 00000e10 0d 0d 20 20 20 20 20 20 20 20 20 20 20 20 20 20 |.. | 00000e20 20 20 44 37 20 20 20 20 20 20 44 36 20 20 20 20 | D7 D6 | 00000e30 20 20 44 35 20 20 20 20 20 20 44 34 20 20 20 20 | D5 D4 | 00000e40 20 20 44 33 20 20 20 20 20 20 44 32 20 20 20 20 | D3 D2 | 00000e50 20 20 44 31 20 20 20 20 20 20 44 30 0d 57 72 69 | D1 D0.Wri| 00000e60 74 65 20 61 74 20 26 46 45 30 35 20 20 30 20 20 |te at &FE05 0 | 00000e70 20 20 20 20 20 30 20 20 20 20 20 20 20 30 20 20 | 0 0 | * 00000e90 20 20 20 20 20 52 32 20 20 20 20 20 20 52 31 20 | R2 R1 | 00000ea0 20 20 20 20 20 52 30 0d 0d 77 68 65 72 65 20 52 | R0..where R| 00000eb0 32 20 52 31 20 52 30 20 73 65 6c 65 63 74 20 77 |2 R1 R0 select w| 00000ec0 68 69 63 68 20 6f 66 20 74 68 65 20 65 69 67 68 |hich of the eigh| 00000ed0 74 20 52 4f 4d 73 20 69 73 20 72 65 71 75 69 72 |t ROMs is requir| 00000ee0 65 64 2e 20 20 54 68 65 73 65 20 65 69 67 68 74 |ed. These eight| 00000ef0 0d 52 4f 4d 73 20 61 72 65 20 6e 75 6d 62 65 72 |.ROMs are number| 00000f00 65 64 20 30 20 74 6f 20 37 2e 0d 0d 4f 6e 63 65 |ed 0 to 7...Once| 00000f10 20 61 67 61 69 6e 2c 20 74 68 65 20 77 72 69 74 | again, the writ| 00000f20 65 20 74 6f 20 26 46 45 30 35 20 6d 75 73 74 20 |e to &FE05 must | 00000f30 62 65 20 64 65 63 6f 64 65 64 20 62 79 20 68 61 |be decoded by ha| 00000f40 72 64 77 61 72 65 20 69 6e 20 74 68 65 0d 65 78 |rdware in the.ex| 00000f50 70 61 6e 73 69 6f 6e 20 6d 6f 64 75 6c 65 20 77 |pansion module w| 00000f60 68 69 63 68 20 73 65 6c 65 63 74 73 20 6f 6e 65 |hich selects one| 00000f70 20 6f 66 20 74 68 65 20 65 69 67 68 74 20 52 4f | of the eight RO| 00000f80 4d 73 2e 0d 0d 53 65 6c 65 63 74 69 6f 6e 20 6f |Ms...Selection o| 00000f90 66 20 61 20 52 4f 4d 20 6e 75 6d 62 65 72 20 30 |f a ROM number 0| 00000fa0 20 74 6f 20 37 20 77 69 6c 6c 20 74 61 6b 65 20 | to 7 will take | 00000fb0 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 66 6f |the following fo| 00000fc0 72 6d 3a 0d 0d 20 20 20 20 20 20 20 20 4c 44 41 |rm:.. LDA| 00000fd0 23 20 20 20 20 20 20 26 30 43 20 20 20 20 20 20 |# &0C | 00000fe0 5c 74 6f 0d 20 20 20 20 20 20 20 20 53 54 41 20 |\to. STA | 00000ff0 20 20 20 20 20 20 26 46 34 20 20 20 20 20 20 5c | &F4 \| 00001000 64 65 73 65 6c 65 63 74 0d 20 20 20 20 20 20 20 |deselect. | 00001010 20 53 54 41 20 20 20 20 20 20 20 26 46 45 30 35 | STA &FE05| 00001020 20 20 20 20 5c 42 41 53 49 43 0d 20 20 20 20 20 | \BASIC. | 00001030 20 20 20 4c 44 41 23 20 20 20 20 20 20 52 4f 4d | LDA# ROM| 00001040 6e 75 6d 62 65 72 0d 20 20 20 20 20 20 20 20 53 |number. S| 00001050 54 41 20 20 20 20 20 20 20 26 46 34 0d 20 20 20 |TA &F4. | 00001060 20 20 20 20 20 53 54 41 20 20 20 20 20 20 20 26 | STA &| 00001070 46 45 30 35 0d 0d 4f 6e 20 70 6f 77 65 72 2d 75 |FE05..On power-u| 00001080 70 2c 20 73 69 64 65 77 61 79 73 20 52 4f 4d 73 |p, sideways ROMs| 00001090 20 61 72 65 20 70 6f 6c 6c 65 64 20 69 6e 20 74 | are polled in t| 000010a0 68 65 20 6f 72 64 65 72 20 31 35 20 74 68 72 6f |he order 15 thro| 000010b0 75 67 68 20 74 6f 20 30 20 74 6f 20 66 69 6e 64 |ugh to 0 to find| 000010c0 0d 74 68 65 20 66 69 72 73 74 20 77 68 69 63 68 |.the first which| 000010d0 20 69 73 20 63 6f 6e 66 69 67 75 72 65 64 20 61 | is configured a| 000010e0 73 20 61 20 6c 61 6e 67 75 61 67 65 20 52 4f 4d |s a language ROM| 000010f0 2e 20 20 45 78 65 63 75 74 69 6f 6e 20 77 69 6c |. Execution wil| 00001100 6c 20 74 68 65 6e 0d 63 6f 6d 6d 65 6e 63 65 20 |l then.commence | 00001110 69 6e 20 74 68 69 73 20 52 4f 4d 2e 20 20 41 73 |in this ROM. As| 00001120 20 42 41 53 49 43 20 69 73 20 52 4f 4d 20 6e 75 | BASIC is ROM nu| 00001130 6d 62 65 72 20 31 30 2f 31 31 2c 20 61 20 52 4f |mber 10/11, a RO| 00001140 4d 20 69 6e 20 61 6e 20 65 78 70 61 6e 73 69 6f |M in an expansio| 00001150 6e 0d 6d 6f 64 75 6c 65 20 77 68 69 63 68 20 69 |n.module which i| 00001160 73 20 72 65 71 75 69 72 65 64 20 74 6f 20 70 6f |s required to po| 00001170 77 65 72 2d 75 70 20 62 65 66 6f 72 65 20 42 41 |wer-up before BA| 00001180 53 49 43 20 6d 75 73 74 20 62 65 20 6e 75 6d 62 |SIC must be numb| 00001190 65 72 65 64 20 31 32 20 74 6f 0d 31 35 2e 0d 0d |ered 12 to.15...| 000011a0
F/+HINT6.m0
F/+HINT6.m1
F/+HINT6.m2
F/+HINT6.m4
F/+HINT6.m5
.